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* ARC: clk: introduce HSDK CGU clock driverEugeniy Paltsev2017-12-111-0/+40
| | | | | | | | | | | | | | Synopsys HSDK clock controller generates and supplies clocks to various controllers and peripherals within the SoC. Each clock has assigned identifier and client device tree nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device tree sources. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* rockchip: rk3128: add device tree fileKever Yang2017-11-301-0/+190
| | | | | | | | | | | | | | Add dts binding header for rk3128, files origin from kernel. Series-Changes: 2 - fix i2c address - add saradc and usb phy node - emmc using fifo mode for there is no dma support in rk3128 emmc - add some clock id in cru.h Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* clk: clk_stm32fx: add clock configuration for mmc usagePatrice Chotard2017-11-291-0/+1
| | | | | | | | | | | | | | | | | MMC block needs 48Mhz source clock, for that we choose to select the SAI PLL. Update also stm32_clock_get_rate() to retrieve the MMC clock source needed in MMC driver. STM32F4 uses a different RCC variant than STM32F7. For STM32F4 sdmmc clocks bit are located into dckcfgr register whereas there are located into dckcfgr2 registers on STM32F7. In both registers, bits CK48MSEL and SDMMC1SEL are located at the same position. Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
* Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblazeTom Rini2017-11-291-0/+30
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx changes for v2018.1 Zynq: - Add support for Syzygy and cc108 boards - Add support for mini u-boot configurations (cse) - dts updates - config/defconfig updates in connection to Kconfig changes - Fix psu_init handling ZynqMP: - SPL fixes - Remove slcr.c - Fixing r5 startup sequence - Add support for external pmufw - Add support for new ZynqMP chips - dts updates - Add support for zcu102 rev1.0 board Drivers: - nand: Support external timing setting and board init - ahci: Fix wording - axi_emac: Wait for bit, non processor mode, readl/write conversion - zynq_gem: Fix SGMII/PCS support
| * arm64: zynqmp: Update device tree for pinmuxMichal Simek2017-11-281-0/+30
| | | | | | | | | | | | | | Added pin control support in device tree for zynqmp. Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | gpio: uniphier: import dt-binginds header from LinuxMasahiro Yamada2017-11-291-0/+18
|/ | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: Synchronize Amlogic from Linux Mainline 4.13.5Neil Armstrong2017-11-171-0/+131
| | | | | | | | | | Synchronize the Amlogic ARM64 dts from mainline Linux 4.13.5 In the preparation of the support of the Amlogic P212 board, import the corresponding meson-gxl-s905x-p212.dts file. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Beniamino Galvani <b.galvani@gmail.com>
* fdt: update bcm283x device tree sources to Linux 4.14 stateAlexander Graf2017-10-162-0/+7
| | | | | | | | | | | | Upstream Linux has received a few device tree updates to the RPi which we should propagate into the builtin U-Boot one as well to gain hardware support. This patch bumps the dts files to their 4.14 Linux counterparts with the exception of sdhost on 32bit RPi versions. There we stay with iproc as the sdhost driver is missing in U-Boot. Signed-off-by: Alexander Graf <agraf@suse.de>
* sunxi: sina33: Sync the device tree with the kernelMaxime Ripard2017-10-032-0/+214
| | | | | | | | | | The kernel DT of the SinA33 has evolved quite a bit. Make sure we sync it and its upstream DTSI to be able to use the OTG. The DTs were taken from the 4.13 kernel release. Reviewed-by: Łukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* rockchip: clk: Add rv1108 SARADC clock supportDavid Wu2017-10-011-0/+2
| | | | | | | | | The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 10-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* ARM: DTS: stm32: adapt stm32h7 dts files for U-bootPatrice Chotard2017-09-221-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adapts stm32h743 disco and eval dts files to match with U-boot requirements or add features wich are not yet upstreamed on kernel side : _ Add RCC clock driver node and update all clocks phandle accordingly. By default, on kernel side, all clocks was temporarly configured as a phandle to timer_clk waiting for a RCC clock driver to be available. On U-boot side, we now have a dedicated RCC clock driver, we can configured all clocks as phandle to this driver. All this binding update will be available soon in a kernel tag, as all the bindings have been acked by Rob Herring [1]. [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html _ Align STM32H7 serial compatible string with the one which will be available in next kernel tag. The bindings has been acked by Rob Herring [2]. This compatible string will be usefull to add stm32h7 specific feature for this serial driver. [2] https://lkml.org/lkml/2017/7/17/739 _ Add gpio compatible and aliases for stm32h743 _ Add FMC sdram node with associated new bindings value to manage second bank (ie bank 1). _ Add missing HSI and CSI oscillators nodes needed by STM32H7 RCC clock driver. Clock sources could be: _ HSE (High Speed External) _ HSI (High Speed Internal) _ CSI (Low Power Internal) These clocks can be used as clocksource in some configuration. By default, HSE is selected as clock source. _ Set HSE to 25Mhz for stm32h743i-disco and eval board By default, the external oscillator frequency is defined at 25 Mhz in SoC stm32h743.dtsi file. It has been set at 125 Mhz in kernel DT temporarly waiting for RCC clock driver becomes available. As in U-boot we got a RCC clock driver, the real value of HSE clock can be used. _ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl, pwrcfg and gpio nodes. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: DTS: stm32: add stm32h743i-disco filesPatrice Chotard2017-09-221-0/+1612
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All these files are imported from linux kernel v4.13 Add device tree support for STM32H743 SoC and discovery board. This board offers : _ STM32H743XIH6 microcontroller with 2 Mbytes of Flash memory and 1 Mbyte of RAM in TFBGA240+25 package _ 5.7” 640x480 TFT color LCD with touch screen _ Ethernet compliant with IEEE-802.3-2002 _ USB OTG HS _ I2 C compatible serial interface _ ST-MEMS digital microphones _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card _ 8Mx32bit SDRAM _ 1-Gbit Twin Quad-SPI NOR Flash _ Reset, wakeup, or key buttons _ Joystick with 4-direction control and selector _ Board connectors : 1 USB with Micro-AB Ethernet RJ45 Stereo headset jack including analog microphone input microSD™ card RCA connector JTAG/SWD and ETM trace _ Expansion connectors: Arduino Uno compatible Connectors 2 x PIO connectors (PMOD and PMOD+) _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: mass storage, virtual COM port and debug port Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: reset: add stm32 reset driverPatrice Chotard2017-09-221-0/+138
| | | | | | | | | | | | | | | | | This driver is adapted from linux drivers/reset/reset-stm32.c It's compatible with STM32 F4/F7/H7 SoCs. This driver doesn't implement .of_match as it's binded by MFD RCC driver. To add support for each SoC family, a SoC's specific include/dt-binfings/mfd/stm32xx-rcc.h file must be added. This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs. Other SoCs support will be added in the future. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: clk: add clk driver support for stm32h7 SoCsPatrice Chotard2017-09-221-0/+167
| | | | | | | | | | | | | | | | | | This driver implements basic clock setup, only clock gating is implemented. This driver doesn't implement .of_match as it's binded by MFD RCC driver. Files include/dt-bindings/clock/stm32h7-clks.h and doc/device-tree-bindings/clock/st,stm32h7-rcc.txt will be available soon in a kernel tag, as all the bindings have been acked by Rob Herring [1]. [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: dts: dra7: sync DT with latest LinuxLokesh Vutla2017-09-111-0/+3
| | | | | | | | | | Sync all dra7* specific dts files with the upstream kernel including changes queued for 4.14 https://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git/log/?h=omap-for-v4.14/dt-v3 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* rockchip: rk3368: add DRAM controller driver with DRAM initialisationPhilipp Tomsich2017-08-131-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a DRAM controller driver for the RK3368 and places it in drivers/ram/rockchip (where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually). At this stage, only the following feature-set is supported: - DDR3 - 32-bit configuration (i.e. fully populated) - dual-rank (i.e. no auto-detection of ranks) - DDR3-1600K speed-bin This driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code). Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time). The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation. As part of this change, DDRC0_CON0 is also added to the GRF structure definition (at offset 0x600). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: dts: rmobile: Import DTS from Linux 4.12Marek Vasut2017-08-035-0/+232
| | | | | | | | | | Import the RCar Gen3 DTS and headers from upstream Linux kernel v4.12-rc6, commit 6f7da290413ba713f0cdd9ff1a2a9bb129ef4f6c . This includes both M3 and H3 ULCB and Salvator-X boards. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* ARM: DTS: stm32: align DT clock declaration with kernelPatrice Chotard2017-07-262-0/+171
| | | | | | | Use the same clocks macro than the one used by kernel DT. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
* arm: dts: meson: import dts files from Linux 4.12Beniamino Galvani2017-07-261-2/+22
| | | | | | | Import Amlogic Meson DTS files from Linux kernel version 4.12 Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-rockchipTom Rini2017-07-111-0/+238
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| * rockchip: rk322x: add dts fileKever Yang2017-07-111-0/+238
| | | | | | | | | | | | | | The dts files are from kernel and with modify to adapt U-Boot. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | ARM64: dts: hi3798cv200-poplar: add device tree bindingsJorge Ramirez-Ortiz2017-07-102-0/+104
|/ | | | | | | Pulled from Linux 4.12-rc3 Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* rockchip: clk: Add rv1108 clock driverAndy Yan2017-06-071-0/+269
| | | | | | | Add clock driver support for Rockchip rv1108 soc Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3368: Add core start-up code for RK3368Andreas Färber2017-06-071-0/+384
| | | | | | | | | | The RK3368 is an octa-core Cortex-A53 SoC from Rockchip. This adds basic support to chain-load U-Boot from Rockchip's miniloader. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-sunxiTom Rini2017-06-032-0/+232
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| * sunxi: A64/Pine64: update device tree from LinuxAndre Przywara2017-06-012-0/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux device tree for the Allwinner A64 SoC has changed a lot since the U-Boot version was merged. Let's replace the current DT with a exact copy of the Linux one as of: commit c6778ff813d2ca3e3c8733c87dc8b6831a64578b Merge: 0ff4c01 3c0e3abd Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Tue May 9 10:07:33 2017 -0700 This is the DT used in Linux 4.12-rc1. Since U-Boot has an Ethernet driver (while Linux does not yet), we provide the required DT nodes for it in an ...-u-boot.dtsi file, to both mark them as U-Boot specific and to allow easier upgrading once Linux gets the driver and its own binding later. Compared to the existing Ethernet DT nodes we just slightly tweak the clock and reset nodes in there to match the new bindings used by Linux for those. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* | MIPS: add support for Broadcom MIPS BCM6338 SoC familyÁlvaro Fernández Rojas2017-05-312-0/+41
| | | | | | | | | | Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | MIPS: add support for Broadcom MIPS BCM3380 SoC familyÁlvaro Fernández Rojas2017-05-312-0/+39
| | | | | | | | | | Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | MIPS: add support for Broadcom MIPS BCM6348 SoC familyÁlvaro Fernández Rojas2017-05-312-0/+44
|/ | | | | Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2017-05-181-0/+454
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| * arm: dts: imx7: sync with LinuxPeng Fan2017-05-181-0/+454
| | | | | | | | | | | | | | | | | | Sync with Linux commit 308ac756("Merge tag 'gpio-v4.11-3'"). Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefan Agner <stefan.agner@toradex.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* | arm: socfpga: Add reset driver support for Arria 10Ley Foon Tan2017-05-181-0/+110
|/ | | | | | | Add reset driver support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2017-05-102-1/+87
|\ | | | | | | | | | | This adds a new firefly-rk3399 board, MIPI support for rk3399 and rk3288, rk818 pmic support, mkimage improvements for rockchip and a few other things.
| * rockchip: dts: rk3399: sync with kernel dtsKever Yang2017-05-102-1/+85
| | | | | | | | | | | | | | | | The kernel dts has update a lot since the first time we commit rk3399.dtsi, sync with kernel for further development. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: dts: evb-rk3399: add gmac supportKever Yang2017-05-101-0/+2
| | | | | | | | | | | | | | Enable gmac for evb-rk3399. Change-Id: I85e35667e08e22e38577e63eb0e65731fc9c69b6 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2017-05-108-0/+224
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| * mips: bmips: add bcm6328-power-domain driver support for BCM63268Álvaro Fernández Rojas2017-05-101-0/+25
| | | | | | | | | | | | This driver can control up to 32 power domains. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
| * mips: bmips: add bcm6328-power-domain driver support for BCM6328Álvaro Fernández Rojas2017-05-101-0/+21
| | | | | | | | | | | | This driver can control up to 32 power domains. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
| * mips: bmips: add bcm6345-rst driver support for BCM63268Álvaro Fernández Rojas2017-05-101-0/+32
| | | | | | | | | | | | | | This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * mips: bmips: add bcm6345-rst driver support for BCM6328Álvaro Fernández Rojas2017-05-101-0/+24
| | | | | | | | | | | | | | This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * mips: bmips: add bcm6345-rst driver support for BCM6358Álvaro Fernández Rojas2017-05-101-0/+21
| | | | | | | | | | | | | | This driver can control up to 32 resets. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * mips: bmips: add bcm6345-clk driver support for BCM63268Álvaro Fernández Rojas2017-05-101-0/+52
| | | | | | | | | | | | | | This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * mips: bmips: add bcm6345-clk driver support for BCM6328Álvaro Fernández Rojas2017-05-101-0/+25
| | | | | | | | | | | | | | This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * mips: bmips: add bcm6345-clk driver support for BCM6358Álvaro Fernández Rojas2017-05-101-0/+24
| | | | | | | | | | | | | | This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | omap3630: Copy Device tree from Linux 4.9.y stableAdam Ford2017-05-091-0/+22
|/ | | | | | | | Add device tree support to allow for CONFIG_OF_CONTROL in OMAP3630 boards. DM3730 can use this same device tree. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* phy: marvell: cp110: add 5G XFI modeIgal Liberman2017-05-091-4/+5
| | | | | | | | | | | | | | | This patch adds the option to configure a comphy to 5G XFI mode. In order to configure the comphy to 5G XFI, update the comphy node in the device-tree: phy2 { phy-type = <PHY_TYPE_SFI>; phy-speed = <PHY_SPEED_5_15625G>; }; Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
* phy: marvell: add IGNORE COMPHY typeStefan Roese2017-05-091-1/+2
| | | | | | | | | | | | | | This type tells u-boot to preserve the COMPHY settings as is it is usefull in situations where the COMPHY was initialized by earlier firmware. Note that IGNORE is different from UNCONNECTED since setting UNCONNECTED type will disconnect the COMPHY in the COMPHY MUX which is a desired behaviour Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* phy: marvell: cp110: update utmi phy connection typeStefan Roese2017-05-091-3/+3
| | | | | | | | | | | UTMI_PHY_TO_USB_HOST was used in USB3 UTMI dts node only, but there will be USB2 UTMI dts node for some SoCs that have got USB2 controller, so rename TO_USB_HOST to TO_USB3_HOST to distinguish TO_USB2_HOST in later on patches. Signed-off-by: zachary <zhangzg@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* phy: marvell: Replace PHY_TYPE_KR with PHY_TYPE_SFIStefan Roese2017-05-091-1/+1
| | | | | | | | Use correct naming as done in the latest Marvell U-Boot version as well. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* aspeed: Add support for Clocks needed by MACsmaxims@google.com2017-05-081-0/+2
| | | | | | | | | | | | | | | | | | | | Add support for clocks needed by MACs to ast2500 clock driver. The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and PCLK_MAC2 for MAC1 and MAC2 respectively. The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed SDK. It is not entirely clear from the datasheet how this clock is used by MACs, so not clear if the rate would ever need to be different. So, for now, hardcoding it is probably safer. The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through hardware strapping. So, the network driver would only need to enable these clocks, no need to configure the rate. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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