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* Merge tag 'xilinx-for-v2021.01-v2' of ↵Tom Rini2020-10-292-0/+165
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.01-v2 common: - Add support for 64bit loadables from SPL xilinx: - Update documentation and record ownership - Enable eeprom board detection based legacy and fru formats - Add support for FRU format microblaze: - Optimize low level ASM code - Enable SPI/I2C - Enable distro boot zynq: - Add support for Zturn V5 zynqmp: - Improve silicon detection code - Enable several kconfig options - Align DT with the latest state - Enabling security commands - Enable and support FPGA loading from SPL - Optimize xilinx_pm_request() calling versal: - Some DTs/Kconfig/defconfig alignments - Add binding header for clock and power zynq-sdhci: - Add support for tap delay programming zynq-spi/zynq-qspi: - Use clock framework for getting clocks xilinx-spi: - Fix some code issues (unused variables) serial: - Check return value from clock functions in pl01x
| * dt-bindings: arm64: versal: Add clk and power headersMichal Simek2020-10-272-0/+165
| | | | | | | | | | | | Add power and reset headers to be sources by Versal dtses. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | drivers: Add a new framework for multiplexer devicesJean-Jacques Hiblot2020-10-281-0/+17
|/ | | | | | | | | | | | Add a new subsystem that handles multiplexer controllers. The API is the same as in Linux. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> [trini: Update some error calls to use different functions or pass correct arguments] Signed-off-by: Tom Rini <trini@konsulko.com>
* reset: ast2500: Use SCU for reset controlChia-Wei, Wang2020-10-221-34/+39
| | | | | | | | | | | | | | | The System Control Unit (SCU) controller of Aspeed SoCs provides the reset control for each peripheral. This patch refactors the reset method to leverage the SCU reset control. Thus the driver dependency on watchdog including dedicated WDT API and reset flag encoding can be eliminated. The Kconfig description is also updated accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* arm: dts: r8a774c0: Import DTS from Linux 5.9Lad Prabhakar2020-10-202-0/+86
| | | | | | | | Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
* pinctrl: Add support for Kendryte K210 FPIOASean Anderson2020-10-081-0/+277
| | | | | | | | | | | The Fully-Programmable Input/Output Array (FPIOA) device controls pin multiplexing on the K210. The FPIOA can remap any supported function to any multifunctional IO pin. It can also perform basic GPIO functions, such as reading the current value of a pin. However, GPIO functionality remains largely unimplemented (in favor of the dedicated GPIO peripherals). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* test: pinmux: Add test for pin muxingSean Anderson2020-10-081-0/+19
| | | | | | | | | | | | | | | | | This extends the pinctrl-sandbox driver to support pin muxing, and adds a test for that behaviour. The test is done in C and not python (like the existing tests for the pinctrl uclass) because it needs to call pinctrl_select_state. Another option could be to add a command that invokes pinctrl_select_state and then test everything in test/py/tests/test_pinmux.py. The pinctrl-sandbox driver now mimics the way that many pinmux devices work. There are two groups of pins which are muxed together, as well as four pins which are muxed individually. I have tried to test all normal paths. However, very few error cases are explicitly checked for. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge tag 'u-boot-amlogic-20201005' of ↵Tom Rini2020-10-064-1/+31
|\ | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - generate unique mac address from SoC serial on S400 board - Add USB support for GXL and AXG SoCs - Update Gadget code to use the new GXL and AXG USB glue driver - Add a VIM3 board support to add dynamic PCIe enable in OS DT - Fix AXG pinmux with requesting GPIOs - Add missing GPIOA_18 for AXG pinctrl - Add Amlogic PWM driver
| * ARM: dts: sync amlogic G12A/SM1 DT from Linux 5.9-rc1Neil Armstrong2020-10-052-0/+12
| | | | | | | | | | | | | | | | | | | | This imports the G12A & SM1 SoC and boards DT changes from the Linux commit 9123e3a74ec7 ("Linux 5.9-rc1"). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * ARM: dts: sync amlogic AXG/GXL/GXM DT from Linux 5.8-rc1Neil Armstrong2020-10-052-1/+19
| | | | | | | | | | | | | | | | | | This imports the AXG, GXL & GXM SoC and boards DT changes from the Linux commit b3a9e3b9622a ("Linux 5.8-rc1"). This change also removes GXL & GXM u-boot.dtsi hacks for USB gadget. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | Merge tag 'u-boot-atmel-2021.01-a' of ↵WIP/05Oct2020-nextTom Rini2020-10-051-0/+22
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for 2021.01 cycle: This feature set includes a new CPU driver for at91 family, new driver for PIT64B hardware timer, support for new at91 family SoC named sama7g5 which adds: clock support, including conversion of the clock tree to CCF; SoC support in mach-at91, pinctrl and mmc drivers update. The feature set also includes updates for mmc driver and some other minor fixes and features regarding building without the old Atmel PIT and the possibility to read a secondary MAC address from a second i2c EEPROM.
| * | clk: at91: add pre-requisite headers for AT91 clock architectureClaudiu Beznea2020-09-221-0/+22
| |/ | | | | | | | | | | | | | | Add pre-requisite headers for AT91 clock architecture. These are based on already present files on Linux and will be used by following commits for AT91 CCF clock drivers. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | Merge branch 'next' of git://git.denx.de/u-boot-sh into nextTom Rini2020-10-016-53/+223
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| * | arm: dts: r8a774e1: Import DTS from Linux 5.9-rc4Biju Das2020-09-262-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | Import R8A774E1 (RZ/G2H) SoC DTSI and headers from upstream Linux kernel 5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
| * | arm: dts: r8a774b1: Import DTS from Linux 5.9-rc4Biju Das2020-09-262-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | Import R8A774B1 (RZ/G2N) SoC DTSI and headers from upstream Linux kernel 5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
| * | arm: dts: r8a774a1: Import DTS from Linux 5.9-rc4Biju Das2020-09-262-53/+45
| | | | | | | | | | | | | | | | | | | | | | | | Synchronize RZ/G2M SoC DTs with mainline Linux 5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
* | | riscv: clk: Add CLINT clock to kendryte clock driverSean Anderson2020-09-301-0/+1
|/ / | | | | | | | | | | | | | | Another "virtual" clock (in the sense that it isn't configurable). This could possibly be done as a clock in the device tree, but I think this is a bit cleaner. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | Merge tag 'xilinx-for-v2021.01' of ↵WIP/24Sep2020-nextTom Rini2020-09-241-0/+40
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.01 arm64: - Support for bigger U-Boot images compiled with PIE microblaze: - Extend support for LE/BE systems zynqmp: - Refactor silicon ID detection code with using firmware interface - Add support for saving variables based on bootmode zynqmp-r5: - Fix MPU mapping and defconfig setting. xilinx: - Minor driver changes: names alignment - Enable UBIFS - Minor DT and macros fixes - Fix boot with appended DT - Fix distro boot cmd: - pxe: Add fixing for platforms with manual relocation support clk: - fixed_rate: Add DM flag to support early boot on r5 fpga: - zynqmppl: Use only firmware interface and enable SPL build serial: - uartlite: Enable for ARM systems and support endians mmc: - zynq: Fix indentation net: - gem: Support for multiple phys - emac: Fix 64bit support and enable it for arm64 kconfig: - Setup default values for Xilinx platforms - Fix dependecies for Xilinx drivers - Source board Kconfig only when platform is enabled - Fix FPGA Kconfig entry with SPL - Change some defconfig values bindings: - Add binding doc for vsc8531
| * | include: dt-bindings: Add MSCC headerHarini Katakam2020-09-231-0/+40
| |/ | | | | | | | | | | | | | | Add MSCC header with delay definitions for VSC8531 and associated family devices. Signed-off-by: Harini Katakam <harini.katakam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | reset: Add IPQ40xx reset controller driverRobert Marko2020-09-181-0/+92
| | | | | | | | | | | | | | | | On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets. So since this will be needed by further drivers, lets add a driver for the reset controller. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | dt-bindings: clock: import Qualcomm IPQ4019 bindingsRobert Marko2020-09-091-0/+96
| | | | | | | | | | | | | | | | Import Qualcomm IPQ4019 GCC bindings from Linux. This will enable using bindings instead of raw clock numbers both in the driver and DTS like Linux does. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | cosmetic: aspeed: Modify for SPDX-LicenseRyan Chen2020-09-091-1/+1
| | | | | | | | | | | | | | Modify SPDX-License for furture patch warning Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
* | clock:aspeed: Sync with Linux kernel clock header defineRyan Chen2020-09-091-28/+40
| | | | | | | | | | | | | | | | | | | | v2: modify title description aspeed:clock -> clock:aspeed Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
* | cosmetic: aspeed: ast2500: Rename clock headerRyan Chen2020-09-091-0/+0
|/ | | | | | | | Rename the ast2500-scu.h to aspeed-clock.h. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
* arm: dts: mt7622: add SATA reset constantsFrank Wunderlich2020-08-191-1/+4
| | | | | | add reset constants used for SATA to header file Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
* dt-bindings: Sync include/dt-bindings/phy/phy.h from LinuxMichal Simek2020-08-041-0/+4
| | | | | | | Add 4 new phy types which are present in Linux kernel. DP and SGMII types are used on Xilinx ZynqMP devices. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini2020-08-041-0/+19
|\ | | | | | | - add DM based reset driver for SiFive SoC's.
| * dt-bindings: prci: add indexes for reset signals available in prciSagar Shrikant Kadam2020-08-041-0/+19
| | | | | | | | | | | | | | | | | | | | | | Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC. The DDR and ethernet sub-system's have reset signals indicated by these reset indexes. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
* | clk: clk_octeon: Add simple MIPS Octeon clock driverStefan Roese2020-08-031-0/+12
|/ | | | | | | | | | This patch adds a simple clock driver for the Marvell Octeon MIPS SoC family. Its for IO clock rate passing via DT in some of the Octeon driver, like I2C. So that we don't need to use the non-mainline API octeon_get_io_clock(). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Lukasz Majewski <lukma@denx.de>
* dt-bindings: pinctrl: add ns3 pads definitionRayagonda Kokatanur2020-07-291-0/+41
| | | | | | | Add NS3 pads definitions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dt-bindings: memory: ns3: add ddr memory definitionRayagonda Kokatanur2020-07-291-1/+30
| | | | | | | Add ddr memory definitions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dt-bindings: memory: ns3: add memory definitionsRayagonda Kokatanur2020-07-291-0/+34
| | | | | | | Add NS3 memory definitions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: dts: r8a774a1: Import DTS from Linux 5.8-rc1Adam Ford2020-07-252-0/+98
| | | | | | | This patch imports the device tree and required bindings to permit the device tree to build for the R8Z774A1 (RZ/G2M). Signed-off-by: Adam Ford <aford173@gmail.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini2020-07-172-0/+38
|\ | | | | | | | | | | | | | | | | | | - New timer API to allow delays with a 32-bit microsecond timer - Add dynamic ACPI structs (DSDT/SSDT) generations to the DM core - x86: Enable ACPI table generation by default - x86: Enable the copy framebuffer on Coral - x86: A few fixes to FSP2 with ApolloLake - x86: Drop setup_pcat_compatibility() - x86: Primary-to-Sideband Bus minor fixes
| * x86: irq: Support flags for acpi_gpeSimon Glass2020-07-171-0/+14
| | | | | | | | | | | | | | | | | | This binding currently has a flags cell but it is not used. Make use of it to create ACPI tables for interrupts. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
| * x86: Add bindings for NHLTSimon Glass2020-07-171-0/+24
| | | | | | | | | | | | | | | | | | Add devicetree bindings for the Intel Non-High-Definition-Audio Link Table (NHLT). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge tag 'u-boot-imx-20200716' of ↵Tom Rini2020-07-171-0/+16
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX for 2020.10 ---------------- - i.MX DDR driver fix/update for i.MX8M - i.MX pinctrl driver fix. - Use arm_smccc_smc to remove imx sip function - i.MX8M clk update - support booting aarch32 kernel on aarch64 hardware - fused part support for i.MX8MP - imx6: pcm058 to DM Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/708734785
| * dts-bindings: regulator: Add dlg,da9063-regulatorNiel Fourie2020-07-141-0/+16
| | | | | | | | | | | | | | | | Add da9063-regulator bindings from Linux 5.6: commit 7111951b8d49 upstream Signed-off-by: Niel Fourie <lusus@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* | arm: dts: k3-am65/j721e: Sync DMA DT bindings from Kernel DTVignesh Raghavendra2020-07-131-31/+0
|/ | | | | | | | Sync DT bindings from kernel DT and move them to out of -u-boot.dtsi files. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
* reset: Add Raspberry Pi 4 firmware reset controllerNicolas Saenz Julienne2020-07-101-0/+13
| | | | | | | | | | | Raspberry Pi 4's co-processor controls some of the board's HW initialization process, but it's up to Linux to trigger it when relevant. Introduce a reset controller capable of interfacing with RPi4's co-processor that models these firmware initialization routines as reset lines. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
* riscv: Add device tree for K210 and Sipeed Maix BitMSean Anderson2020-07-011-0/+38
| | | | | | | | | Where possible, I have tried to find compatible drivers based on the layout of registers. However, many devices remain untested. All untested devices have been left disabled, but some tentative properties (such as compatible strings, and clocks, interrupts, and resets properties) have been added. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* clk: Add K210 clock supportSean Anderson2020-07-012-0/+97
| | | | | | | | | | Due to the large number of clocks, I decided to use the CCF. The overall structure is modeled after the imx code. Clocks parameters are stored in several arrays, and are then instantiated at run-time. There are some translation macros (FOOIFY()) which allow for more dense packing. Signed-off-by: Sean Anderson <seanga2@gmail.com> CC: Lukasz Majewski <lukma@denx.de>
* omap5: Copy device tree from linux 5.7.yTero Kristo2020-06-161-0/+129
| | | | | | | Copy all the device tree files required for omap5 uevm support from mainline Linux. Signed-off-by: Tero Kristo <t-kristo@ti.com>
* omap4: Copy device tree from Linux 5.7.yTero Kristo2020-06-161-0/+149
| | | | | | | Copy all device tree files required for omap4 panda support from mainline Linux. Signed-off-by: Tero Kristo <t-kristo@ti.com>
* dt-bindings: input: adopt Linux gpio-keys binding constantsPeter Robinson2020-05-311-0/+13
| | | | | | Sync the gpio-keys input bindings from linux 5.7-rc1. Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
* dt-bindings: imx_rsrc: add SC_R_NONEPeng Fan2020-05-101-0/+1
| | | | | | Add SC_R_NONE entry Signed-off-by: Peng Fan <peng.fan@nxp.com>
* phy: atheros: add device tree bindings and configMichael Walle2020-05-071-0/+13
| | | | | | | | | | | | | | | | | Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge tag 'u-boot-imx-20200502' of ↵Tom Rini2020-05-041-2/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX for 2020.07 ---------------- - imxrt: fix LCD clock, fix doc - new board: Coral Dev - imx8: enable Cache in SPL. SNVS, update SCFW API - imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading - MX6ULL : is_imx6ull to include i.MX6ULZ - Net: add config to enable TXC delay Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914
| * dt-bindings: pinctrl: imxrt1020: remove useless commentGiulio Benetti2020-05-011-2/+0
| | | | | | | | | | | | | | A comment note has been left after completing pinctrl listing, so let's remove it since it's useless. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* | Merge tag 'u-boot-rockchip-20200501' of ↵Tom Rini2020-05-042-106/+125
|\ \ | |/ |/| | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - dts clean up to use -u-boot for px30, rk3399 boards - dts sycn from upstream kernel for rk3328, rk3399 - add rockchip rng driver - new board support: rk3328-roc-cc, rk3399-roc-pc,Nanopi M4 2GB
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