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* Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2019-03-211-5/+1
|\ | | | | | | - i2c: i2c_cdns: Fix below warnings with checker tool
| * i2c: i2c_cdns: Fix below warnings with checker toolSiva Durga Prasad Paladugu2019-03-211-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes below warnings found with checker tool. The variable len in i2c_msg struct is of unsigned type and it is received as recv_count which is unsigned type but it is checked with < 0 which is always false, hence removed it. The local variable curr_recv_count is declared as signed type and compared aginst unsigned recv_count which is incorrect. This is fixed by declaring it as unsigned type. drivers/i2c/i2c-cdns.c: In function ‘cdns_i2c_read_data’: drivers/i2c/i2c-cdns.c:317:18: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if ((recv_count < 0)) ^ drivers/i2c/i2c-cdns.c:340:24: warning: comparison of integer expressions of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’ [-Wsign-compare] updatetx = recv_count > curr_recv_count; ^ drivers/i2c/i2c-cdns.c:361:39: warning: comparison of integer expressions of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’ [-Wsign-compare] while (readl(&regs->transfer_size) != Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | Merge git://git.denx.de/u-boot-marvellTom Rini2019-03-193-5/+12
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Enable network interface on clearfog_gt_8k (Baruch) - Fix dreamplug boot by adding an spi0 alias to the DT (Chris) - Fix / enhance Marvell ddr3 setup / parameters (Chris) - Change CONFIG_SYS_MALLOC_F_LEN to 0x2000 on db-88f6820-amc (Chris) - Enable SPL_FLASH_BAR on db-88f6820-amc (Chris) - Use correct pcie controller name in Armada-38x dts files (Chris) - Disable d-cache on Kirkwood platforms as currently needed (Chris) - Add a more descriptive comment to pci_mvebu.c (Stefan) - Update Marvell maintainers entry (Stefan)
| * | mv_ddr: ddr3: only use active chip-selects when tuning ODTChris Packham2019-03-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Inactive chip-selects will give invalid values for read_sample so don't consider them when trying to determine the overall min/max read sample. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> [https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/18] Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | mv_ddr: ddr3: fix tRAS timimg parameterChris Packham2019-03-191-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the JEDEC standard JESD79-3F. The tRAS timings should include the highest speed bins at a given frequency. This is similar to commit 683c67b ("mv_ddr: ddr3: fix tfaw timimg parameter") where the wrong comparison was used in the initial implementation. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> [https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/15] Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | pci: pci_mvebu: Add comment about missing of_n_addr_cells() callStefan Roese2019-03-191-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a comment to explain the use of the hardcoded value for the number of address cells in mvebu_get_tgt_attr(). This should help to rework this function, once CONFIG_OF_LIVE is enabled for MVEBU in general. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2019-03-192-3/+6
|\ \ \ | |/ / |/| | | | | - Fastboot fixes
| * | fastboot: common: fix default fastboot_boot on 64-bitNeil Armstrong2019-03-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting on a 64-bit system, the boot_addr_start buffer is not large enough to contain a 64-bit number, thus leading to a crash even if fastboot_buf_addr is valid, only the high part of the address will be printed to boot_addr_start : fastboot with fastboot_buf_addr = 0x0000000006000000: downloading of 92239872 bytes finished Booting kernel at 0x00000000... "Synchronous Abort" handler, esr 0x96000004 elr: 00000000010561f4 lr : 0000000001056fac (reloc) <snip> x28: 000000007df2d38f x29: 000000007df2d1b0 Resetting CPU ... With this fix, boot_addr_start can have the full 64-bit address passed to bootm. Fixes: f73a7df984a9 ("net: fastboot: Merge AOSP UDP fastboot") Cc: Simon Glass <sjg@chromium.org> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | usb: udc-uclass: Fixed problem when no alias is defined in DTJean-Jacques Hiblot2019-03-161-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 801f1fa442 "dm: usb: udc: Use SEQ_ALIAS to index the USB gadget ports" changed the way the udevice if found. It uses the alias to find a udevice for a given USB port number. In the commit log it was stated that if no alias is provided, the bind order will be used instead. However it doesn't work. Fixing this by adding a call to uclass_get_device() if uclass_get_device_by_seq() fails. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Tested-by: Vignesh R <vigneshr@ti.com>
* | | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2019-03-153-9/+25
|\ \ \ | |/ / |/| | | | | - DPAA2 fixes and DDR errata workaround for LS1021A
| * | drivers: net: ls1088ardb: Fix EC1 and EC2 RCW offsetPramod Kumar2019-03-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Fix EC1 and EC2 read from correct offset 26, instead of 25 Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | mc : Reduce MC memory size to 128MMeenakshi Aggarwal2019-03-151-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | ls2088, ls1088 : minimum MC Memory size is 128 MB lx2 : minimum MC memory size is 256 MB Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | driver: net: fsl-mc: Fix DPC MAC address fixupIoana Ciocoi Radulescu2019-03-151-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If node /board_info/ports does not exist in the DPC file, function mc_fixup_dpc() will skip not only MAC address fixup, but also the cache flush at the end. This may cause the other fixup changes (e.g. ICID related ones) to be ignored by MC. Fixes: 1161dbcc0a36 ("drivers: net: fsl-mc: Include MAC addr fixup to DPL") Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | drivers: net: ldpaa_eth: check if the dpmac is enabledPankaj Bansal2019-03-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2019-03-143-4/+60
|\ \ \ | |/ / |/| |
| * | power: regulator: s2mps11: Add enable delayKrzysztof Kozlowski2019-03-111-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | According to datasheet, the output on LDO regulators will start appearing after 10-15 us. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | regulator: Add support for ramp delayKrzysztof Kozlowski2019-03-111-2/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changing voltage and enabling regulator might require delays so the regulator stabilizes at expected level. Add support for "regulator-ramp-delay" binding which can introduce required time to both enabling the regulator and to changing the voltage. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | power: regulator: s2mps11: Fix step for LDO27 and LDO35Krzysztof Kozlowski2019-03-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | LDO27 and LDO35 have 25 mV step, not 50 mV. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Lukasz Majewski <lukma@denx.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | adc: exynos-adc: Fix wrong bit operation used to stop the ADCKrzysztof Kozlowski2019-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | When stopping the ADC_V2_CON1_STC_EN should be cleared. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Lukasz Majewski <lukma@denx.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge tag 'u-boot-imx-20190313' of git://git.denx.de/u-boot-imxTom Rini2019-03-136-21/+61
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Small fixes in several i.MX boards ---------------------------------- - imx8: add pinctrl driveri (mx8m), fix documentation and fix reported CPU frequency. Fabio is co-maintainer - pico-imx6ul: switch to DM - local fixes for ventana, mx6ul_14x14_evk, engicam, imx6(q)_logic, liteboard
| * | | drivers/net/fec: phy_init: remove redundant logicHannes Schmelzer2019-03-131-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The phy_connect_dev(...) function from phy.c does all the handling (inclusive catching fixed-link). So we drop here the single steps and call just phy_connect_dev(...). Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | MTD: mxs_nand_spl: Redo the way nand_init initializesAdam Ford2019-03-131-11/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the spl system calls nand_init which does nothing. It isn't until an attempt to load from NAND that it gets initialized. Subsequent attempts to load just skip the initialization because NAND is already initialized. This moves the contents of mxs_nand_init to nand_init. In the event of an error, it clears the number of nand chips found. Any attempts to use nand will check if there are nand chips available instead of actually doing the initialization at that time. If there are none, it will return an error to the higher level calls. Signed-off-by: Adam Ford <aford173@gmail.com>
| * | | imx: serial_mxc: use CONFIG_IS_ENABLED instead of ifdefAdam Ford2019-03-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kconfig allows boards to configured with DM_SERIAL and still have SPL_DM_SERIAL disabled. This patch changes the ifdef's to CONFIG_IS_ENABLED to allow the modes to differ between SPL and U-Boot. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | pinctrl: add imx8m driverPeng Fan2019-03-133-0/+51
| | |/ | |/| | | | | | | | | | | | | Add i.mx8m pinctrl driver. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | | Merge tag 'efi-2019-04-rc4-2' of https://github.com/xypron2/u-bootTom Rini2019-03-121-1/+22
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | Pull request for UEFI system for v2019.04-rc4 Fix an error with the serial communication on boards with a very small UART buffer which leads to a stalled system. Provide an X86 reset driver for the UEFI runtime.
| * | x86: Add efi runtime resetAlexander Graf2019-03-111-1/+22
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our selftest will soon test the actual runtime reset function rather than the boot time one. For this, we need to ensure that the runtime version actually succeeds on x86 to keep our travis tests work. So this patch implements an x86 runtime reset function. It is missing shutdown functionality today, but OSs usually implement that via ACPI and this function does more than the stub from before, so it's at least an improvement. Eventually we will want to have full DM functionality in runtime services. But this fixes a travis failure and doesn't clutter the code too heavily, so we should pull it in without the amazing new RTS DM framework. Signed-off-by: Alexander Graf <agraf@suse.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2019-03-119-1/+22
|\ \ | | | | | | | | | | | | - axp818 fix - fix warnings for ethernet clock code
| * | clk: sunxi: h3: Implement EPHY CLK and RESETJagan Teki2019-03-091-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EPHY CLK and RESET is available in Allwinner H3 EMAC via mdio-mux node of internal PHY. Add the respective clock and reset reg and bits. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | clk: sunxi: Implement EMAC, GMAC clocks, resetsJagan Teki2019-03-096-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Implement EMAC, GMAC clocks via ccu_clk_gate for all supported Allwinner SoCs. - Implement EMAC, GMAC resets via ccu_reset for all supported Allwinner SoCs. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | clk: sunxi: Implement A10 EMAC clocksJagan Teki2019-03-092-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC. Which would eventually used in sunxi_emac.c driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | power: axp818: Fix typo in axp_set_dldoOndrej Jirman2019-03-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix typo in axp_set_dldo() so that it correctly uses AXP818_DLDO1_CTRL register to configure the voltage instead of setting AXP818_ELDO1_CTRL register which is obviously incorrect. Signed-off-by: Ondřej Jirman <megous@megous.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | | ddr: socfpga: Clean up ddr_setup()Marek Vasut2019-03-091-28/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the current rather convoluted code using ad-hoc polling mechanism with a more straightforward code. Use wait_for_bit_le32() to poll the DDRCALSTAT register instead of local reimplementation. It makes no sense to pull for 5 seconds before giving up and trying to restart the EMIF, so instead wait 500 mSec for the calibration to complete and if this fails, restart the EMIF and try again. Perform this 32 times instead of 3 times as the original code did. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* | | ddr: socfpga: Clean up EMIF resetMarek Vasut2019-03-091-26/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EMIF reset code can well use wait_for_bit_le32() instead of all that convoluted polling code. Reduce the timeout from 100 seconds to 1 second, since if the EMIF fails to reset itself in 1 second, it's unlikely longer wait would help. Make sure to clear the EMIF reset request even if the SEQ2CORE_INT_RESP_BIT isn't asserted. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* | | ddr: socfpga: Fix EMIF clear timeoutMarek Vasut2019-03-091-14/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current EMIF clear timeout handling code was applying bitwise operations to signed data types and as it was, was extremely hard to read. Replace it with simple wait_for_bit(). Expand the error handling to make it more readable too. This patch also changes the timeout for emif_clear() from 14 hours to 1 second. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* | | ddr: socfpga: Fix newline in debug print on A10Marek Vasut2019-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The debug print is missing a newline, add it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* | | ddr: socfpga: Fix IO in Arria10 DDR driverMarek Vasut2019-03-091-3/+3
| |/ |/| | | | | | | | | | | | | | | | | | | | | The Altera Arria10 DDR driver was using constants in a few places instead of reading registers associated with those constants, fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2019-03-083-57/+129
|\ \ | |/ |/| | | | | | | | | | | This pull request contains bugfixes for rcar_i2c, rcar_ii2c and i2c_cdns driver. Also the commit "i2c: rcar_i2c: Add Gen3 SoC support" from Marek is a bugfix for arm64 builds, as discussed with Marek on list.
| * i2c: rcar_i2c: Move FSDA check to rcar_i2c_recoverIsmael Luceno Cortes2019-03-081-5/+6
| | | | | | | | | | | | | | Cosmetic change. Any call to the recover function would need to do the same check afterwards, so it's sensible to make it part of the function. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
| * i2c: rcar_i2c: Set the slave address from rcar_i2c_xferIsmael Luceno Cortes2019-03-081-9/+5
| | | | | | | | | | | | | | | | | | It needs to be done for both reads and writes, so do it at rcar_i2c_xfer to avoid duplication. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * i2c: rcar_i2c: Don't mask errors with EREMOTEIO at rcar_i2c_xferIsmael Luceno Cortes2019-03-081-1/+1
| | | | | | | | | | | | | | | | | | | | Fix rcar_i2c_xfer return value, previously it was always returning -EREMOTEIO when dealing with errors from calls to the read/write functions. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * i2c: rcar_i2c: Fix sending of slave addressesIsmael Luceno Cortes2019-03-081-1/+3
| | | | | | | | | | | | | | | | | | Do the reset before clearing the MSR, otherwise it may result in a read or write operation instead if the start condition is repeated. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * i2c: rcar_i2c: Add comments about registers & valuesIsmael Luceno Cortes2019-03-081-21/+26
| | | | | | | | | | | | | | | | | | Document the meaning of macros related to registers and values to be written to them. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * i2c: rcar_i2c: Setup SCL/SDA delay at rcar_i2c_set_speedIsmael Luceno Cortes2019-03-081-3/+6
| | | | | | | | | | | | | | | | | | Setting up the delay only needs to be done once; move it to rcar_i2c_set_speed so it's done at initialization time. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * i2c: i2c_cdns: Add support for handling arbitration lostSiva Durga Prasad Paladugu2019-03-081-13/+53
| | | | | | | | | | | | | | | | | | | | This patch adds support for handling arbitration lost in case of multi master mode. When an arbitration lost is detected, it retries for 10 times before failing. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * i2c: i2c_cdns: Fix clearing of all interruptsSiva Durga Prasad Paladugu2019-03-081-1/+11
| | | | | | | | | | | | | | | | | | | | | | The arbitration lost interrupt was not getting cleared while clearing interrupts. This patch fixes this by adding arbitration lost interrupt as well during clear. This patch also removes hardcoded value and defined a macro for it. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * i2c: rcar_i2c: Add Gen3 SoC supportMarek Vasut2019-03-071-5/+18
| | | | | | | | | | | | | | | | | | Add support for R-Car Gen3 SoCs into the driver, which encompases the Gen3 SoC extra timing register handling and 64bit build fixes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
| * i2c: rcar_iic: Read ICSR only onceMarek Vasut2019-03-071-2/+4
| | | | | | | | | | | | | | | | | | | | | | Read ICSR only once to avoid missing interrupts. This happens on R8A7791 Porter during reset, when reading the PMIC register 0x13, which may fail sometimes because of the missed DTE interrupt. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Heiko Schocher <hs@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2019-03-0615-141/+417
|\ \ | |/ |/| | | | | - dw spi include file fix - Allwinner A31 spi, been in ML in many releases.
| * spi: Rename sun4i_spi.c into spi-sunxi.cJagan Teki2019-03-043-6/+8
| | | | | | | | | | | | | | | | | | | | | | Now the same SPI controller driver is reusable in all Allwinner SoC variants, so rename the existing sun4i_spi.c into spi-sunxi.c which eventually look like a common sunxi driver. Also update the function, variable, structure names in driver from sun4i into sunxi. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: sun4i: Driver cleanupJagan Teki2019-03-041-110/+80
| | | | | | | | | | | | | | | | | | | | - drop unused macros. - use base instead of base_addr, for better code readability - move .probe and .ofdata_to_platdata functions in required places to add platdata support in future. - use sentinel sun4i_spi_ids. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
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