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* Merge tag 'uniphier-v2020.04-2' of ↵WIP/31Jan2020Tom Rini2020-01-315-31/+52
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier UniPhier SoC updates for v2020.04 (2nd) Denali NAND driver changes: - Set up more registers in denali-spl for SOCFPGA - Make clocks optional - Do not assert reset signals in the remove hook - associate SPARE_AREA_SKIP_BYTES with DT compatible - switch to UCLASS_MTD UniPhier platform changes: - fix a bug in dram_init() - specify loadaddr for "source" command
| * mtd: rawnand: denali_dt: use UCLASS_MTD instead of UCLASS_MISCMasahiro Yamada2020-02-012-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | UCLASS_MTD is a better fit for NAND drivers. Make NAND_DENALI_DT depend on DM_MTD, which is needed to compile drivers/mtd/mtd-uclass.c Also, make ARCH_UNIPHIER select DM_MTD because all the defconfig of this platform enables NAND_DENALI_DT. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: denali: set SPARE_AREA_SKIP_BYTES based on DT compatibleMasahiro Yamada2020-02-012-9/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the denali NAND driver in U-Boot configures the SPARE_AREA_SKIP_BYTES based on the CONFIG option. Recently, Linux kernel merged a patch that associates the proper value for this register with the DT compatible string. Do likewise in U-Boot too. The denali_spl.c still uses CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * mtd: rawnand: denali_dt: insert udelay() after reset deassertMasahiro Yamada2020-02-011-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | When the reset signal is de-asserted, the HW-controlled bootstrap starts running unless it is disabled in the SoC integration. It issues some commands to detect a NAND chip, and sets up registers automatically. Until this process finishes, software should avoid any register access. Without this delay function, some of UniPhier boards hangs up while executing nand_scan_ident(). (denali_read_byte() is blocked) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * mtd: rawnand: denali: Do not reset the block before booting the kernelMarek Vasut2020-02-012-13/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Denali NAND driver in mainline Linux currently cannot deassert the reset. The upcoming Linux 5.6 will support the reset controlling, and also set up SPARE_AREA_SKIP_BYTES correctly. So, the Denali driver in the future kernel will work without relying on any bootloader or firmware. However, we still need to take care of stable kernel versions for a while. U-boot should not assert the reset of this controller. Fixes: ed784ac3822b ("mtd: rawnand: denali: add reset handling") Signed-off-by: Marek Vasut <marex@denx.de> [yamada.masahiro: reword the commit description] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * mtd: rawnand: denali_dt: make the core clock optionalMasahiro Yamada2020-02-011-4/+6
| | | | | | | | | | | | | | | | | | The "nand_x" and "ecc" clocks are currently optional. Make the core clock optional in the same way. This will allow platforms with no clock driver support to use this driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Marek Vasut <marex@denx.de> # On SoCFPGA Arria V
| * mtd: rawnand: denali-spl: Add missing hardware init on SoCFPGAMarek Vasut2020-02-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Altera SoCFPGA, upon either cold-boot or power-on reset, the Denali NAND IP is initialized by the BootROM ; upon warm-reset, the Denali NAND IP is NOT initialized by BootROM. In fact, upon warm-reset, the SoCFPGA BootROM checks whether the SPL image in on-chip RAM is valid and if so, completely skips re-loading the SPL from the boot media. This does sometimes lead to problems where the software left the boot media in inconsistent state before warm-reset, and because the BootROM does not reset the boot media, the boot media is left in this inconsistent state, often until another component attempts to access the boot media and fails with an difficult to debug failure. To mitigate this problem, the SPL on Altera SoCFPGA always resets all the IPs on the SoC early on boot. This results in a couple of register values, pre-programmed by the BootROM, to be lost during this reset. To restore correct operation of the IP on SoCFPGA, these values must be programmed back into the controller by the driver. Note that on other SoCs which do not use the HW-controlled bootstrap, more registers may have to be programmed. This also aligns the SPL behavior with the full Denali NAND driver, which sets these values in denali_hw_init(). Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | net: fix typoFlavio Suligoi2020-01-301-1/+1
| | | | | | | | Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
* | Merge tag 'for-v2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2cWIP/29Jan2020Tom Rini2020-01-2922-161/+355
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i2c changes for 2020.04 - updates the Designware I2C driver - get timings from device tree - handle units in nanoseconds - make sure that the requested bus speed is not exceeded - few smaller clean-ups - adds enums for i2c speed and update drivers which use them - global_data: remove unused mxc_i2c specific field
| * | i2c: designware_i2c: Do more in the probe() methodSimon Glass2020-01-271-8/+8
| | | | | | | | | | | | | | | | | | | | | Move some of the code currently in the ofdata_to_platdata() method to probe() so that it is not executed when generating ACPI tables. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | i2c: designware_i2c: Separate out the speed calculationSimon Glass2020-01-272-33/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to be able to calculate the speed separately from actually setting the speed, so we can generate the required ACPI tables. Split out the calculation into its own function. Drop the double underscore on __dw_i2c_set_bus_speed while we are here. That is reserved for compiler internals. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | i2c: designware_i2c: Move dw_i2c_speed_config to headerSimon Glass2020-01-272-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is used to store the speed information for a bus. We want to provide this to ACPI so that it can tell the kernel. Move this struct to the header file so it can be accessed by the ACPI i2c implementation being added later. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | i2c: designware_i2c: Add support for fast-plus speedSimon Glass2020-01-272-2/+12
| | | | | | | | | | | | | | | | | | Fast-plus runs at 1MHz and is used by some devices. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | i2c: Update drivers to use enum for speedSimon Glass2020-01-2714-26/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the obvious uses of i2c bus speeds to use the enum. Use livetree access for code changes. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: stm32: Update to use standard enums for speedSimon Glass2020-01-271-27/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update this driver to use the new standard enums for speed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: omap: Update to use standard enums for speedSimon Glass2020-01-272-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update this driver to use the new standard enums for speed. Note: This driver needs to move to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: kona_i2c: Update to use standard enums for speedSimon Glass2020-01-271-17/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update this driver to use the new standard enums for speed. Note: This driver needs to move to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: designware_i2c: Update to use standard enums for speedSimon Glass2020-01-272-18/+5
| | | | | | | | | | | | | | | | | | | | | Update this driver to use the new standard enums for speed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: ast_i2c: Update to use standard enums for speedSimon Glass2020-01-272-3/+1
| | | | | | | | | | | | | | | | | | | | | Update this driver to use the new standard enums for speed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: designware_i2c: Add spike supressionSimon Glass2020-01-273-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | Some versions of this peripheral include a spike-suppression phase of the bus. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: designware_i2c: Rewrite timing calculationSimon Glass2020-01-271-22/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the driver can end up with timing parameters which are slightly faster than those expected. It is possible to optimise the parameters to get the best possible result. Create a new function to handle the timing calculation. This uses a table of defaults for each speed mode rather than writing it in code. The function works by calculating the 'period' of each bit on the bus in terms of the input clock to the controller (IC_CLK). It makes sure that the constraints are met and that the different components of that period add up correctly. This code was taken from coreboot which has ended up with this same driver, but now in a much-different form. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: designware_i2c: Put hold config in a structSimon Glass2020-01-271-27/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | Create a struct to hold the three timing parameters. This will make it easier to move these calculations into a separate function in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: designware_i2c: Drop scl_sda_cfg parameterSimon Glass2020-01-271-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of passing this parameter into __dw_i2c_set_bus_speed(), pass in the driver's private data, from which the function can obtain that information. This allows the function to have access to the full state of the driver. Signed-off-by: Sicomp_param1mon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | i2c: designware_i2c: Read device-tree propertiesSimon Glass2020-01-273-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | The i2c controller defines a few timing properties. Read these in and store them for use by the driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: designware_i2c: Use an accurate bus clock instead of MHzSimon Glass2020-01-272-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the driver uses an approximation for the bus clock, e.g. 166MHz instead of 166 2/3 MHz. This can result in small errors in the resulting I2C speed, perhaps 0.5% or so. Adjust the existing code to start from the accurate figure, even if later rounding reduces this accuracy. Update the bus speed code to work in KHz instead of MHz, which removes most of the error. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: designware_i2c: Use an enum for selected speed modeSimon Glass2020-01-272-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Group these #defines into an enum to make it easier to understand the relationship between them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jun Chen <ptchentw@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: designware_i2c: Rename 'max' speed to 'high' speedSimon Glass2020-01-272-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SoCs support a higher speed than what is currently called 'max' in this driver. Rename it to 'high' speed, which is the official name of the 3.4MHz speed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jun Chen <ptchentw@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: designware_i2c: Include clk.h in the header fileSimon Glass2020-01-272-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use struct clk here so really should include this header file to avoid build errors. Also switch the order of clk.h in the C file to match the required code style. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jun Chen <ptchentw@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: designware_i2c: Don't allow changing IC_CLKSimon Glass2020-01-271-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | If a different input clock is required then the correct way to do this is with a clock driver. Don't allow boards to override IC_CLK. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | i2c: designware_i2c: Add more registersSimon Glass2020-01-271-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some versions of this peripherals provide more control of the bus behaviour. Add definitions for these registers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jun Chen <ptchentw@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsungTom Rini2020-01-281-0/+5
|\ \ \ | |_|/ |/| | | | | - Various exynos fixes
| * | mmc: s5p_sdhci: Read generic MMC properties from DTMarek Szyprowski2020-01-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read generic MMC properties from device-tree. This allows to specify for example cd-inverted property and let MMC core to properly handle such case. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spiWIP/27Jan2020Tom Rini2020-01-2712-231/+1265
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - spi cs accessing slaves (Bin Meng) - spi prevent overriding established bus (Marcin Wojtas) - support speed in spi command (Marek Vasut) - add W25N01GV spinand (Robert Marko) - move cadence_qspi to use spi-mem (Vignesh Raghavendra) - add octal mode (Vignesh Raghavendra)
| * | | spi: cadence-qspi: Add compatible for TI AM654Vignesh Raghavendra2020-01-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TI's AM654 SoC has a Cadence OSPI IP. Add a new compatible string for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | spi: cadence-qspi: Add support for Cadence Octal SPI controllerVignesh Raghavendra2020-01-272-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cadence OSPI is similar to QSPI IP except that it supports Octal IO (8 IO lines) flashes. Add support for Cadence OSPI IP with existing driver using new compatible Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | mtd: spi-nor-core: Add octal mode supportVignesh Raghavendra2020-01-274-2/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Octal flash devices. Octal flash devices use 8 IO lines for data transfer. Currently only 1-1-8 Octal Read mode is supported. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | spi: cadence-qspi: Add direct mode supportVignesh Raghavendra2020-01-273-33/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | spi: cadence_qspi: Move to spi-mem frameworkVignesh Raghavendra2020-01-273-178/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | mtd: spinand: winbond: Add support for W25N01GVRobert Marko2020-01-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux has supported W25N01GV for a long time, so lets import it. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | spi: ti_qspi: Add support for CS other than CS0Vignesh Raghavendra2020-01-271-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure corresponding setup registers are updated depending on CS. This ensures that driver can support QSPI flashes on ChipSelects other than on CS0 Reported-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | spi: prevent overriding established bus settingsMarcin Wojtas2020-01-271-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPI stack relies on a proper bus speed/mode configuration by calling dm_spi_claim_bus(). However the hitherto code allowed to accidentally override those settings in the spi_get_bus_and_cs() routine. The initially established speed could be discarded by using the slave platdata, which turned out to be an issue on the platforms whose slave maximum supported frequency is not on par with the maximum frequency of the bus controller. This patch fixes above issue by configuring the bus from spi_get_bus_and_cs() only in case it was not done before. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | dm: spi: Check cs number before accessing slavesBin Meng2020-01-271-19/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add chip select number check in spi_find_chip_select(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
| * | | spi: nxp_fspi: new driver for the FlexSPI controllerMichael Walle2020-01-273-0/+1004
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a port of the kernel's spi-nxp-fspi driver. It uses the new spi-mem interface and does not expose the more generic spi-xfer interface. The source was taken from the v5.3-rc3 tag. The port was straightforward: - remove the interrupt handling and the completion by busy polling the controller - remove locks - move the setup of the memory windows into claim_bus() - move the setup of the speed into set_speed() - port the device tree bindings from the original fspi_probe() to ofdata_to_platdata() There were only some style change fixes, no change in any logic. For example, there are busy loops where the return code is not handled correctly, eg. only prints a warning with WARN_ON(). This port intentionally left most functions unchanged to ease future bugfixes. This was tested on a custom LS1028A board. Because the LS1028A doesn't have proper clock framework support, changing the clock speed was not tested. This also means that it is not possible to change the SPI speed on LS1028A for now (neither is it possible in the linux driver). Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Kuldeep Singh <kuldeep.singh@nxp.com>
* | | | power: regulator: add driver for Dialog DA9063 PMICMartin Fuzzey2020-01-273-0/+409
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the regulators in the the DA9063 PMIC. Robert Beckett: move regulator modes to header so board code can set modes. Correct mode mask used in ldo_set_mode. Add an option CONFIG_SPL_DM_REGULATOR_DA9063. Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
* | | | power: pmic: add driver for Dialog DA9063 PMICMartin Fuzzey2020-01-273-0/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the basic register access operations and child regulator binding (if a regulator driver exists). Robert Beckett: simplify accesses by using bottom bit of address as offset overflow. This avoids the need to track which page we are on. Add an option CONFIG_SPL_DM_PMIC_DA9063. Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
* | | | rtc: s35392a: encode command correctlyIan Ray2020-01-271-11/+18
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | The 3-bit "command", or register, is encoded within the device address. Configure the device accordingly, and pass command in DM I2C read/write calls correctly. Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
* | | Merge tag 'u-boot-clk-26Jan2020' of ↵Tom Rini2020-01-277-11/+28
|\ \ \ | |_|/ |/| | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-clk - Various clock fixes and enhancements
| * | clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate()Giulio Benetti2020-01-261-2/+8
| | | | | | | | | | | | | | | | | | | | | Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate()Giulio Benetti2020-01-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate()Giulio Benetti2020-01-261-2/+8
| | | | | | | | | | | | | | | | | | | | | Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
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