summaryrefslogtreecommitdiff
path: root/drivers
Commit message (Collapse)AuthorAgeFilesLines
* Merge https://source.denx.de/u-boot/custodians/u-boot-spiTom Rini2021-08-033-10/+24
|\ | | | | | | | | - SPI-NOR fix (Big Meng) - XMC XM25QH64C flash (Reto Schneider)
| * mtd: spi-nor: Mask out fast read if not requested in DTBin Meng2021-08-031-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DT bindings of "jedec,spi-nor" [1] defines "m25p,fast-read" property to indicate that "fast read" opcode can be used to read data from the chip instead of the usual "read" opcode. If this property is not present in DT, mask out fast read in spi_nor_init_params(). This change mirrors the same logic in spi_nor_info_init_params() in drivers/mtd/spi-nor/core.c in the Linux kernel v5.14-rc3. [1] Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml in the kernel tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi-nor: Respect flash's hwcaps in spi_nor_adjust_hwcaps()Bin Meng2021-08-031-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | The smart spi_nor_adjust_hwcaps() does not respect the SPI flash's hwcaps, and only looks to the controller on what can be supported. The flash's hwcaps needs to be AND'ed before checking. Fixes: 71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: spi-mem-nodm: Fix read data size issueBin Meng2021-08-031-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | When slave drivers don't set the max_read_size, the spi-mem should directly use data.nbytes and not limit to any size. But current logic will limit to the max_write_size. This commit mirrors the same changes in the dm version done in commit 535b1fdb8e5e ("spi: spi-mem: Fix read data size issue"). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi-nor-ids: Add support for XMC XM25QH64CReto Schneider2021-08-031-0/+1
| | | | | | | | | | | | | | | | | | | | This chip has been (briefly) tested on the MediaTek MT7688 based GARDENA smart gateway. Datasheet: http://xmcwh.com/Uploads/2020-12-17/XM25QH64C_Ver1.1.pdf Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | Merge https://source.denx.de/u-boot/custodians/u-boot-x86Tom Rini2021-08-023-8/+11
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | - Fixed broken ICH SPI driver in software sequencer mode - Added "m25p,fast-read" to SPI flash node for x86 boards - Drop ROM_NEEDS_BLOBS and BUILD_ROM for x86 ROM builds - Define a default TSC timer frequency for all x86 boards - x86 MTRR MSR programming codes bug fixes - x86 "hob" command bug fixes - Don't program MTRR for DRAM for FSP1 - Move INIT_PHASE_END_FIRMWARE to FSP2 - Use external graphics card by default on Intel Crown Bay - tangier: Fix DMA controller IRQ polarity in CSRT
| * x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQBin Meng2021-08-022-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently there are two places to specify the x86 TSC timer frequency with one in Kconfig used for early timer and the other one in device tree used when the frequency cannot be determined from hardware. This may potentially create an inconsistent config where the 2 values do not match. Let's use the one specified in Kconfig in the device tree as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * spi: ich: Limit slave->max_read_sizeBin Meng2021-08-021-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()") (in v2020.04-rc1), SPI flash read no longer works with ICH SPI controller in software sequencer mode. ICH controller can only transfer a small number of bytes at once. Before commit 43c145b8b3ee, the logic happens to make sure data.nbytes is limited to slave->max_write_size but after commit 43c145b8b3ee data.nbytes is no longer limited because slave->max_read_size is not initialized with a valid number. Fixes: 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | global: Convert simple_strtoul() with decimal to dectoul()Simon Glass2021-08-0224-39/+38
| | | | | | | | | | | | | | It is a pain to have to specify the value 10 in each call. Add a new dectoul() function and update the code to use it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | global: Convert simple_strtoul() with hex to hextoul()Simon Glass2021-08-0219-43/+42
| | | | | | | | | | | | | | | | | | It is a pain to have to specify the value 16 in each call. Add a new hextoul() function and update the code to use it. Add a proper comment to simple_strtoul() while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge tag 'efi-2021-10-rc2' of ↵Tom Rini2021-08-021-14/+12
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2021-10-rc2 Documentation: * handle 'make htmldocs' warnings as errors * add missing board/ti/index.rst Bug fixes: * avoid buffer overrun in TrueType console * lib: disable CONFIG_SPL_HEXDUMP by default
| * | video: buffer overrun in TrueType consoleHeinrich Schuchardt2021-08-011-14/+12
| |/ | | | | | | | | | | | | | | When scrolling the TrueType console a buffer overrun occurs. Fixes: a29b012037cc ("video: Add a console driver that uses TrueType fonts") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge tag 'mmc-2021-7-30' of https://source.denx.de/u-boot/custodians/u-boot-mmcTom Rini2021-08-023-29/+38
|\ \ | | | | | | | | | | | | pl180_mmci update and cleanup fix rpmb routing memory alignment
| * | mmc: arm_pl180_mmci: Add configuration for ST-Ericsson Ux500v2Stephan Gerhold2021-07-302-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the eMMC on ST-Ericsson Ux500v2 we need slightly different configuration values. Use the existing switch statement to match the peripheral ID of Ux500v2 (0x10480180) and override the necessary values to make the eMMC work on devices with ST-Ericsson Ux500. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> on stm32f769-disco Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: arm_pl180_mmci: Simplify code using mmc_of_parse()Stephan Gerhold2021-07-301-15/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify the code a bit by using the common mmc_of_parse() function instead of duplicating the device tree parsing code. We can still get a default value for cfg->f_max by assigning it before calling mmc_of_parse(). Another advantage of this refactoring is that we parse more properties now, e.g. "non-removable" can be used to disable CD entirely. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> on stm32f769-disco Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: arm_pl180_mmci: Simplify code using dev_read_addr_ptr()Stephan Gerhold2021-07-301-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify the code a bit by using dev_read_addr_ptr() instead of dev_read_addr(). This avoids having to cast explicitly to void*. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> on stm32f769-disco Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: arm_pl180_mmci: Don't bind to all arm, primecell devicesStephan Gerhold2021-07-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The arm,primecell compatible is used for lots of different types of devices, e.g. I2C, SPI, coresight, ... We really should not bind the MMC driver to all of them. Looking through the device trees in U-Boot there seems to be always a second compatible string for the pl180 device, either arm,pl180 (already listed) or arm,pl18x. Add the "arm,pl18x" compatible to the list but remove the generic "arm,primecell". Note that on Linux these compatibles cannot be found in drivers because AMBA/primecell devices are matched based on their peripheral ID instead of the compatible. This fixes the following error messages when booting the ST-Ericsson U8500 "stemmy" board with the arm_pl180_mmci driver enabled: MMC: ptm@801ae000 - probe failed: -38 ptm@801af000 - probe failed: -38 funnel@801a6000 - probe failed: -38 tpiu@80190000 - probe failed: -38 etb@801a4000 - probe failed: -38 Cc: Patrice Chotard <patrice.chotard@st.com> Fixes: 6f41d1a17e20 ("mmc: arm_pl180_mmci: Sync compatible with kernel") Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> on stm32f769-disco Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: rpmb: Fix driver routing memory alignment with tmp bufferlitchipi2021-07-301-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix mmc_rpmb_route_frames() implementation to comply with most MMC drivers that expect some alignment of MMC data frames in memory. When called from drivers/tee/optee/rpmb.c, the address passed is not aligned properly. OP-TEE OS inserts a 6-byte header before a raw RPMB frame which makes RPMB data buffer not 32bit aligned. To prevent breaking ABI with OPTEE-OS RPC memrefs, allocate a temporary buffer to copy the data into an aligned memory. Many RPMB drivers implicitly expect 32bit alignment of the eMMC frame including arm_pl180_mmci.c, sandbox_mmc.c and stm32_sdmmc2.c Signed-off-by: Timothée Cercueil <timothee.cercueil@st.com> Signed-off-by: Timothée Cercueil <litchi.pi@protonmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | sandbox: tpm: Support extending a PCR multiple timesSimon Glass2021-08-011-14/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is fairly easy to handle this case and it makes the emulator more useful, since PCRs are commonly extended several times. Add support for this, using U-Boot's sha256 support. For now sandbox only supports a single PCR, but that is enough for the tests that currently exist. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | sandbox: tpm: Correct handling of SANDBOX_TPM_PCR_NBSimon Glass2021-08-011-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the number of PCRs, so the current check is off by one. Also the map itself should not be checked, just the resulting pcr_index, to avoid confusing people who read the code. Fix these problems. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | sandbox: tpm: Support storing device state in tpm2Simon Glass2021-08-011-0/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the tpm2 emulator does not support storing the device state. Add this so we can handle the normal vboot flow through the sandbox executables (VPL->SPL etc.) with the TPM contents staying in place. Note: sandbox has not yet been converted to use livetree for the state information, since livetree does not yet support writing to the tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | sandbox: tpm: Support nvdata in TPM2Simon Glass2021-08-011-0/+68
| | | | | | | | | | | | | | | | | | | | | Add support for this feature in the TPM2 emulator, to support Chromium OS vboot. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | sandbox: tpm: Track whether the state is validSimon Glass2021-08-011-2/+8
| | | | | | | | | | | | | | | | | | | | | Add checking as to whether the current TPM state is valid, so we can implement reading/writing the state. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | sandbox: tpm: Finish comments for struct sandbox_tpm2Simon Glass2021-08-011-4/+16
| | | | | | | | | | | | | | | | | | Tidy up the missing comments for this struct. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | sandbox: tpm: Correct handling of get-capabilitySimon Glass2021-08-011-10/+4
| | | | | | | | | | | | | | | | | | | | | This function current handles the kernel case incorrectly. Fix it, and use the shorter TPM_HDR_LEN while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | sandbox: tpm: Support the define-space commandSimon Glass2021-08-013-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | Add support for this command, moving away from the previous approach of hard-coding the initial data in the driver, now that the kernel-space data has to be set up by the higher-level vboot code. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | sandbox: tpm: Tidy up reading and writing of device stateSimon Glass2021-08-011-11/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present this code assumes that the TPM data has been read but this may not be the case. Refactor the code to use a separate pointer so we know the current state of the data. Add error checking for the data size. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | sandbox: tpm: Split out common nvdata codeSimon Glass2021-08-014-105/+172
| |/ |/| | | | | | | | | | | | | | | | | We want to support nvdata in TPM2 as well. To avoid code duplicating the associated code, move it into a common file. Drop the special-case logic for the kernel space. This can be handled by the higher-level code now, i.e. in vboot itself. Signed-off-by: Simon Glass <sjg@chromium.org>
* | serial: a37xx: Do not call get_ref_clk() in _debug_uart_init()Pali Rohár2021-07-311-1/+3
| | | | | | | | | | | | | | | | | | | | Static inline function _debug_uart_init() should avoid calling external (non-inline) functions. Therefore do not call get_ref_clk() in _debug_uart_init() and reimplement its functionality without external function calls. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
* | serial: a37xx: Use CONFIG_BAUDRATE for initializing early debug UARTPali Rohár2021-07-311-3/+2
| | | | | | | | | | | | | | | | | | CONFIG_BAUDRATE should be used for setting the baudrate for the early debug UART. This replaces current hardcoded 115200 value. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* | arm64: a37xx: pinctrl: Correct PWM pins definitionsMarek Behún2021-07-311-9/+8
|/ | | | | | | | | | | | | | | | | | | | | | | The PWM pins on North Bridge on Armada 37xx can be configured into PWM or GPIO functions. When in PWM function, each pin can also be configured to drive low on 0 and tri-state on 1 (LED mode). The current definitions handle this by declaring two pin groups for each pin: - group "pwmN" with functions "pwm" and "gpio" - group "ledN_od" ("od" for open drain) with functions "led" and "gpio" This is semantically incorrect. The correct definition for each pin should be one group with three functions: "pwm", "led" and "gpio". Change the "pwmN" groups to support "led" function. Remove "ledN_od" groups. This cannot break backwards compatibility with older device trees: no device tree uses it since there is no PWM driver for this SOC yet. Also "ledN_od" groups are not even documented. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* Merge branch '2021-07-28-assorted-fixes'Tom Rini2021-07-291-2/+11
|\ | | | | | | - Assorted bugfixes
| * pci: swap_case: Allow compilation on 32-bit machinesSimon Glass2021-07-281-2/+11
| | | | | | | | | | | | | | | | | | At present this driver assumes that ulong is 64-bits long. On 32-bit machines it is not. Use the 64-bit code only on 64-bit machines. This makes things work correctly on 32-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge tag 'ti-v2021.10-rc2' of ↵Tom Rini2021-07-2912-0/+4415
|\ \ | |/ |/| | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-ti - Add MMC High speed modes for AM64 and J7200 - Add Sierra/Torrent SERDES driver - Minor clean-ups for R5F boot from SPL
| * phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoCJean-Jacques Hiblot2021-07-275-0/+1168
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com
| * phy: cadence: Add driver for Torrent SERDESAswath Govindraju2021-07-273-0/+2470
| | | | | | | | | | | | | | | | | | Add driver for Torrent SERDES. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-9-kishon@ti.com
| * phy: cadence: Add driver for Sierra PHYAlan Douglas2021-07-275-0/+760
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a Sierra PHY driver with PCIe and USB support. This driver is a port from the mainline linux driver. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY One difference with the linux driver is that the PHY is always reset after it is powered-on. This is because role switching is not supported in u-boot and the cable orientation is handled by the PHY reset. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-8-kishon@ti.com
| * dm: core: Add helper to compare node namesKishon Vijay Abraham I2021-07-271-0/+13
| | | | | | | | | | | | | | | | | | Add helper to compare node names. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20210721155849.20994-2-kishon@ti.com
| * mmc: sdhci_am654: Read ti, strobe-sel property from device treeAswath Govindraju2021-07-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | Read the strobe select value from the device tree property ti,strobe-sel, required for HS400 speed mode Fixes: a20008eabd95 ("mmc: am654_sdhci: Add Support for configuring PHY in J721e") Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Link: https://lore.kernel.org/r/20210525093826.10390-2-a-govindraju@ti.com
| * mmc: sdhci: Write to HOST_CONTROL2 register for HS400 speed modeFaiz Abbas2021-07-271-0/+3
| | | | | | | | | | | | | | | | | | | | Enable HS400 speed mode by writing to HOST_CONTROL2 register. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Link: https://lore.kernel.org/r/20210405144428.12159-1-a-govindraju@ti.com
* | Makefile: Move drivers/i2c/ into drivers/MakefileSimon Glass2021-07-281-4/+0
| | | | | | | | | | | | | | | | | | | | This rule should not be in the top-level Makefile. Now that we have a consistent set of I2C Kconfigs for U-Boot proper, SPL and TPL, we can move it. Make use of the existing SPL/TPL rule in drivers/Makefile instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* | i2c: Rename SPL/TPL_I2C_SUPPORT to I2CSimon Glass2021-07-281-1/+5
| | | | | | | | | | | | | | Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* | i2c: Create a new Kconfig for I2CSimon Glass2021-07-281-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present we have CONFIG_SPL_I2C but not CONFIG_I2C. The reason CONFIG_I2C is not strictly necessary is that: a) We have CONFIG_SYS_I2C_LEGACY and CONFIG_DM_I2C for the two possible i2c stacks b) In U-Boot proper, we always build drivers/i2c/ regardless of the options Still, it is better to have CONFIG_I2C - it makes U-Boot proper similar to SPL/TPL, so we can (in a future commit) simplify the Makefile rules. Enable it by default, since as above, we have separate options (SYS_I2C_LEGACY and DM_I2C) to control whether it is 'really' enabled. Once we have migrated I2C to driver model, we can drop SYS_I2C_LEGACY and make DM_I2C become I2C. For now, this lets us simplify the Makefile rules. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* | i2c: Rename CONFIG_SYS_I2C to CONFIG_SYS_I2C_LEGACYSimon Glass2021-07-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It is quite confusing that CONFIG_SYS_I2C selects the legacy I2C and CONFIG_DM_I2C selects the current I2C. The deadline to migrate I2C is less than a year away. Also we want to have a CONFIG_I2C for U-Boot proper just like we have CONFIG_SPL_I2C for SPL, so we can simplify the Makefile rules. Rename this symbol so it is clear it is going away. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* | Rename DRIVERS_MISC_SUPPORT to DRIVERS_MISCSimon Glass2021-07-281-1/+1
| | | | | | | | | | | | Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Rename GPIO_SUPPORT to GPIOSimon Glass2021-07-286-9/+9
| | | | | | | | | | | | Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Rename SPL_USB_HOST_SUPPORT to SPL_USB_HOSTSimon Glass2021-07-285-9/+9
| | | | | | | | | | | | Rename this option so that CONFIG_IS_ENABLED can be used with it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Rename SPL_WATCHDOG_SUPPORT to SPL_WATCHDOGSimon Glass2021-07-281-1/+1
| | | | | | | | | | | | Rename this option so that CONFIG_IS_ENABLED can be used with it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Rename SPL_MUSB_NEW_SUPPORT to SPL_MUSB_NEWSimon Glass2021-07-281-1/+1
| | | | | | | | | | | | Rename this option so that CONFIG_IS_ENABLED can be used with it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Rename SPL_ETH_SUPPORT to SPL_ETHSimon Glass2021-07-281-2/+2
| | | | | | | | | | | | Rename this option so that CONFIG_IS_ENABLED can be used with it. Signed-off-by: Simon Glass <sjg@chromium.org>
View Lorry Controller Status