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* x86: apl: Add PMC driverSimon Glass2019-12-151-0/+56
| | | | | | | | Add a driver for the Apollo Lake SoC. It supports the basic operations and can use device tree or of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a generic Intel GPIO driverSimon Glass2019-12-153-0/+171
| | | | | | | | | Add a GPIO driver which uses the pinctrl driver to access the pad information. This driver relies on the GPIO nodes being subnodes to the pinctrl device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a generic Intel pinctrl driverSimon Glass2019-12-155-0/+667
| | | | | | | | | | | | | | | Recent Intel SoCs share a pinctrl mechanism with many common elements. Add an implementation of this core functionality, allowing SoC-specific drivers to avoid adding common code. As well as a pinctrl driver this provides a GPIO driver based on the same code. Once other SoCs use this driver we may consider moving more properties to the device tree (e.g. the community info and pad definitions). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* mtd: spi: Export spi_flash_std_probe()Simon Glass2019-12-151-1/+1
| | | | | | | | | | | | With of-platdata we need to create drivers for particular chips, or at least drivers that are separate from the standard code, since C structures are created by dtoc which are private to that driver. To avoid duplicating the probing code, export this probe function for use by these drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spi: ich: Add Apollo Lake supportSimon Glass2019-12-152-5/+15
| | | | | | | | Add support for Apollo Lake to the ICH driver. This involves adjusting the mmio address and skipping setting of the bbar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spi: ich: Add TPL supportSimon Glass2019-12-151-4/+44
| | | | | | | | | In TPL we want to reduce code size and support running with CONFIG_PCI disabled. Add special code to handle this using a fixed BAR programmed into the SPI on boot. Also cache the SPI flash to speed up boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spi: ich: Add support for get_mmap() methodSimon Glass2019-12-151-0/+32
| | | | | | | | Add this method so that the memory-mapped location of the SPI flash can be queried. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spi: ich: Support hardware sequencingSimon Glass2019-12-152-3/+245
| | | | | | | | Apollo Lake (APL) only supports hardware sequencing. Add support for this into the SPI driver, as an option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spi: ich: Support of-platdata for fast-spiSimon Glass2019-12-151-3/+15
| | | | | | | | The Intel Fast SPI interface is similar to ICH. Add of-platdata support for this using the "intel,fast-spi" compatible string. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spi: ich: Correct max-size bug in ich_spi_adjust_size()Simon Glass2019-12-151-3/+5
| | | | | | | | This incorrectly shortens read operations if there is a maximum write size but no maximum read size. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spi: ich: Add mmio_base to struct ich_spi_platdataSimon Glass2019-12-152-19/+13
| | | | | | | | | It is useful to store the mmio base in platdata. It reduces the amount of casting needed. Update the code and move the struct to the C file at the same time, as we will need to use with of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spi: ich: Various small tidy-upsSimon Glass2019-12-151-9/+8
| | | | | | | | | Use debug() instead of printf() to reduce code size and change a bool return value to the use the 'bool' type. Also drop the global data declaration since it not actually used. Finally, set the log category. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spi: ich: Fix header orderSimon Glass2019-12-151-2/+2
| | | | | | | Move the header files into the right order. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spi: ich: Convert to livetreeSimon Glass2019-12-151-17/+5
| | | | | | | | Use dev_get_driver_data() to obtain the device type. It has the same effect and is shorter. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spi: ich: Move the protection/lockdown code into a functionSimon Glass2019-12-152-20/+44
| | | | | | | | | | | | Reduce the size of the probe function but putting this code into its own function. Also remove the assumption that the PCH is always a parent of the SPI controller, as this is not the case APL platforms. Use driver model to find the PCH instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spi: ich: Move init function just above probe()Simon Glass2019-12-151-61/+61
| | | | | | | | | It is annoying to have some of the init code in a different part of the file. Move ich_init_controller() to just above probe() to keep things together. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: spi: Don't enable SPI_FLASH_BAR by defaultSimon Glass2019-12-151-1/+0
| | | | | | | | | | | We don't normally need this on x86 unless the size of SPI flash devices is larger than 16MB. This can be enabled by particular SoCs as needed, since it adds to code size. Drop the default enabling of this option on x86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spi: Correct operations check in dm_spi_xfer()Simon Glass2019-12-152-9/+5
| | | | | | | | At present we have to have an xfer() method even if it does nothing. This is not correct, so fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow removal of standard PCH driversSimon Glass2019-12-152-2/+20
| | | | | | | | These drivers are not needed on all platforms. While they are small, it is useful in TPL to drop then. Add Kconfig control to allow this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* sandbox: Add a test for IRQSimon Glass2019-12-152-0/+56
| | | | | | | Add a simple sandbox test for this uclass. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move UCLASS_IRQ into a separate fileSimon Glass2019-12-153-0/+63
| | | | | | | | | | | Update this uclass to support the needs of the Apollo Lake ITSS. It supports four operations. Move the uclass into a separate directory so that sandbox can use it too. Add a new Kconfig to control it and enable this on x86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* sandbox: Add PCI driver and test for p2sbSimon Glass2019-12-154-0/+373
| | | | | | | | Add a sandbox driver and PCI-device emulator for p2sb. Also add a test which uses a simple 'adder' driver to test the p2sb functionality. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Add support for p2sb uclassSimon Glass2019-12-153-0/+250
| | | | | | | | | | | | | The Primary-to-Sideband bus (P2SB) is used to access various peripherals through memory-mapped I/O in a large chunk of PCI space. The space is segmented into different channels and peripherals are accessed by device-specific means within those channels. Devices should be added in the device tree as subnodes of the p2sb. This adds a uclass and enables it for sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: sandbox: Add a PMC emulator and testSimon Glass2019-12-155-0/+354
| | | | | | | Add a simple PMC for sandbox to permit tests to run. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: power: Add an ACPI PMC uclassSimon Glass2019-12-154-0/+220
| | | | | | | | | Intel x86 SoCs have a power manager/controller which handles several power-related aspects of the platform. Add a uclass for this, with a few useful operations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: timer: Reduce timer code size in TPL on Intel CPUsSimon Glass2019-12-152-2/+14
| | | | | | | | | | | | | | | Most of the timer-calibration methods are not needed on recent Intel CPUs and just increase code size. Add an option to use the known-good way to get the clock frequency in TPL. Size reduction is about 700 bytes. Note that version 1 of this commit caused bootstage to crash since the CPU was not identified. This is corrected by changes previously applied to make sure that the CPU is identified before spl_init() is called, such as 39146a2e0b x86: Move CPU init to before spl_init() Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: timer: use a timer base of 0Simon Glass2019-12-152-1/+16
| | | | | | | | | | | | | | | | On x86 platforms the timer is reset to 0 when the SoC is reset. Having this as the timer base is useful since it provides an indication of how long it takes before U-Boot is running. When U-Boot sets the timer base to something else, time is lost and we no-longer have an accurate account of the time since reset. This particularly affects bootstage. Change the default to not read the timer base, leaving it at 0. Add an option for when U-Boot is the secondary bootloader. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pinctrl: Allow enabling full pinctrl in SPL/TPLSimon Glass2019-12-151-0/+14
| | | | | | | | At present these options cannot be enabled for SPL/TPL, but this can be useful in some cases. Add Kconfig options to allow it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* i2c: designware: Support use in SPLSimon Glass2019-12-151-3/+40
| | | | | | | | | | | | Allow this driver to set up an IO address in SPL using an 'early-regs' property. This allows SPL to use the I2C driver without having to enable the full PCI stack. Also split out ofdata_to_platdata in designware driver since this is more correct, and more convenient for the new logic. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* i2c: designware: Avoid using static dataSimon Glass2019-12-151-3/+6
| | | | | | | | | | | Drivers are not allowed to use static data since they may be used in SPL where BSS is not available. It is possible that driver model may provide support for numbering devices in the future. But for now, move this to global_data. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* i2c: designware: Tidy up PCI supportSimon Glass2019-12-154-89/+134
| | | | | | | | | | | | | | | | This is hacked into the driver at present. It seems better to have it as a separate driver that uses the base driver. Create a new file and put the X86 code into it. Actually the Baytrail settings should really come from the device tree. Note that 'has_max_speed' is added as well. This is currently always false but since only Baytrail provides the config, it does not affect operation for other devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Move pci_get_devfn() into a common fileSimon Glass2019-12-152-16/+20
| | | | | | | | | | | | | | | Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Allow delaying auto-config until after relocationSimon Glass2019-12-151-5/+10
| | | | | | | | | | | | | | At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: gpio: Allow control of GPIO uclass in SPLSimon Glass2019-12-1526-67/+94
| | | | | | | | | | | | | | | | | | | | At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge tag 'dm-next-13dec19' of ↵Tom Rini2019-12-122-2/+2
|\ | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next buildman improvements including toolchain environment feature sandbox unicode support in serial
| * cros_ec: use uint instead of uint8_t for cmd paramMichael Auchter2019-12-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Chromium EC commands can be up to 16-bits, so using a uint8_t here can cause truncation. Update to use a uint instead. It looks like this should likely have been done as a part of 9fea76f5d30264dc08ac591a7a89427b8441555b, but this function was skipped for some reason. Signed-off-by: Michael Auchter <michael.auchter@ni.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * serial: sandbox: support UnicodeHeinrich Schuchardt2019-12-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | Due to a conversion error the sandbox does not accept byte values 0x80-0xff from the keyboard. The UEFI extended text input unit test requires Unicode support. Use unsigned char for the serial buffer. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
* | Merge tag 'fix-for-2020.01' of ↵WIP/11Dec2019Tom Rini2019-12-111-1/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-i2c i2c bugfixes for 2020.01 - i2c: i2c_cdns: fix write timeout on fifo boundary fixes timout issue when writting number of bytes is multiple of the FIFO depth.
| * | i2c: i2c_cdns: fix write timeout on fifo boundaryMichael Auchter2019-12-111-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes an issue that would cause I2C writes to timeout when the number of bytes is a multiple of the FIFO depth (i.e. 16 bytes). Within the transfer loop, after writing the data register with a new byte to transfer, if the transfer size equals the FIFO depth, the loop pauses until the INTERRUPT_COMP bit asserts to indicate data has been sent. This same check is performed after the loop as well to ensure data has been transferred prior to returning. In the case where the amount of data to be written is a multiple of the FIFO depth, the transfer loop would wait for the INTERRUPT_COMP bit to assert after writing the final byte, and then wait for this bit to assert once more. However, since the transfer has finished at this point, no new data has been written to the data register, and hence INTERRUPT_COMP will never assert. Fix this by only waiting for INTERRUPT_COMP in the transfer loop if there's still data to be written. Signed-off-by: Michael Auchter <michael.auchter@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge tag 'u-boot-atmel-fixes-2020.01-a' of ↵Tom Rini2019-12-111-3/+26
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel - First set of u-boot-atmel fixes for 2020.01 cycle: This set includes a small fix for gpio bank names, one for removing unused headers (also touches some other boards), and a fix for the QSPI env read on one of the boards.
| * | gpio: at91_gpio: Add bank namesJames Byrne2019-12-031-3/+26
| | | | | | | | | | | | | | | | | | | | | | | | Make the at91_gpio driver set sensible GPIO bank names in the platform data. This makes the 'gpio status' command a lot more useful. Signed-off-by: James Byrne <james.byrne@origamienergy.com> Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
* | | Merge tag 'fixes-for-2020.01' of ↵WIP/10Dec2019Tom Rini2019-12-105-16/+24
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-video - fix crash and board reset when drawing RLE8 bitmaps bigger than the framebuffer resolution - reduce dead code in video and console uclass routines (tested on mx53cx9020, sama5d2_xplained, stm32mp157c-ev1, stm32f746-disco, stm32f769-disco and wandboard)
| * | video: make BPP and ANSI configs optionalAnatolij Gustschin2019-12-062-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many boards do not use all selected framebuffer depth configurations, for such boards there is some unused code in video and console uclass routines. Make depth specific code optional to avoid dead code and slightly reduce binary size. Also make ANSI code optional for the same reason. When i.e. using only VIDEO_BPP16 the code size shrinks (below values when using gcc-7.3.0): $ ./tools/buildman/buildman -b video-wip -sS wandboard ... 01: Merge git://git.denx.de/u-boot-sh 02: video: add guards around 16bpp/32bbp code 03: video: make BPP and ANSI configs optional arm: (for 1/1 boards) all -776.0 bss -8.0 text -768.0 Signed-off-by: Anatolij Gustschin <agust@denx.de> Tested-by: Eugen Hristev <eugen.hristev@microchip.com> Tested-by: Patrice Chotard <patrice.chotard@st.com> Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
| * | video: add guards around 16bpp/32bbp codeAnatolij Gustschin2019-12-062-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many boards use only single depth configuration, for such boards there is some unused code in video and console uclass routines. Add guards to avoid dead code. Signed-off-by: Anatolij Gustschin <agust@denx.de> Tested-by: Eugen Hristev <eugen.hristev@microchip.com> Tested-by: Patrice Chotard <patrice.chotard@st.com> Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
| * | video: bmp: Fix video_display_rle8_bitmap()Patrice Chotard2019-12-061-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case the BMP size is bigger than the frame buffer, don't use the BMP's width and height in video_display_rle8_bitmap, but the one's checked in video_bmp_display() as parameters to video_display_rle8_bitmap(). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> CC: Yannick Fertré <yannick.fertre@st.com>
| * | video: bmp: Fix video_splash_align_axis()Patrice Chotard2019-12-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert panel_picture_delta and axis_alignment from unsigned long to long to insure to store correctly the difference between panel_size and picture_size in case the panel_size is smaller than picture_size. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> CC: Yannick Fertré <yannick.fertre@st.com> [agust: change axis_alignment to long] Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini2019-12-091-0/+1
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Increase stack size to avoid a stack overflow during distro boot. - Add hifive-unleashed-a00.dts for SIFIVE FU540. - Add OF_SEPARATE support for SIFIVE FU540. - Add SPL support for Andes AX25 AE350. - Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
| * | | spl: cache: Allow cache drivers in SPLRick Chen2019-12-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When ax25-ae350 try to enable v5l2 cache driver in SPL configuration, it need this option for cache support in SPL. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
* | | | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-netWIP/09Dec2019Tom Rini2019-12-0918-442/+749
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| * | | net: ti: am65-cpsw-nuss: Add new compatible for J721eVignesh Raghavendra2019-12-092-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new compatible to handle J721e SoC Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
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