summaryrefslogtreecommitdiff
path: root/drivers
Commit message (Collapse)AuthorAgeFilesLines
* watchdog MediaTek add upstream compatibleMatthias Brugger2020-05-011-0/+1
| | | | | | | The upstream compatible is called mt6589-wdt. Add this compatible to the driver. Signed-off-by: Matthias Brugger <mbrugger@suse.com>
* timer MediaTek use upstream compatibleMatthias Brugger2020-05-011-0/+1
| | | | | | | The timers compatible string in upstream is called mt6577-timer. Add this compatible to the driver. Signed-off-by: Matthias Brugger <mbrugger@suse.com>
* rtc: pcf2127: don't add/subtract 1 to tm_monRasmus Villemoes2020-05-011-2/+2
| | | | | | | | | | | | As noted in rtc_def.h, the tm_mon field in struct rtc_time is 1-12, unlike in struct tm where it is 0-11. Currently, running "date" prints the wrong Date: 2020-04-01 (Friday) Time: 13:05:30 and setting the RTC via the date command is also broken. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spiWIP/30Apr2020Tom Rini2020-04-3011-1176/+982
|\ | | | | | | | | - distro boot support for SPI flash - sifive spi flash driver
| * spi: sifive: Fix QPP transferJagan Teki2020-04-301-20/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The guessed reason is that the existing logic of filling tx fifo with data, rx fifo with NULL for tx transfer and filling rx fifo with data, tx fifo with NULL for rx transfer is not clear enough to support the Quad Page Program.     SiFive SPI controllers have specific sets of watermark registers and SPI I/O directions bits in order to program SPI controllers clear enough to support all sets of operating modes.     Here is the exact programing sequence that would follow on this patch and tested via SPI-NOR and MMC_SPI.     - set the frame format proto, endian - set the frame format dir, set it for tx and clear it for rx - TX transfer:   fill tx fifo with data.   wait for TX watermark bit to clear. - RX transfer:   fill tx fifo with 0xff.   write nbytes to rx watermark register   wait for rx watermark bit to clear.   read the rx fifo data. So, this patch adopts this program sequence and fixes the existing I/O direction bit. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
| * spi: sifive: Fix format register proto fieldJagan Teki2020-04-301-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SiFive SPI controller has a proto bit field in frame format register which would be used to configure the SPI I/O protocol lines used on specific transfer.  Right now the driver is configuring this proto using slave->mode, for all types of transctions. This makes the driver unable to function since the proto needs to configure dynamically for each and every transaction separately at runtime. Now, the controller driver supports per transfer via spi-mem exec_opo, so add the fmt_proto flag and fill the per transfer buswidth so that the controller configures the proto bit at runtime. This patch fixes the SPI controller works with SPI NOR flash on quad read with page program. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
| * spi: sifive: Add spi-mem exec opJagan Teki2020-04-301-1/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SiFive SPI controller is responsible to handle the slave devices like mmc spi and spi nor flash. The controller is designed such a way that it would handle the slave transactions based on the I/O protocol numbers, example if spi nor slave send quad write opcode it has to send alone with I/O protocol number of 4 and if it try to send data it has to send I/O protocol number along with 4 line data. But the current spi-xfer code from spi-mem is combining the opcode and address in a single transaction, so the SPI controller will be unable to identify the I/O protocol number of opcode vs address. So, add the spi-mem exec_op with spi-xfer of opcode, address and data as a separate transaction. This doesn't remove the .xfer of dm_spi_ops since mmc spi will make use of it. Note: This code might have moved to the spi-mem core area once we have done the dedicated tests on other controllers and have real reason to move. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
| * mtd: spi-nor-ids: Add Spansion s25fs512s flash entryKuldeep Singh2020-04-301-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Spansion "s25fs512s" flash is incorrectly decoded as "s25fl512s" on various platforms as former is not present. Add the entry. Linux already has both the flashes present. A snippet below: { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256...}, { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256...}, Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * watchdog: kconfig: Enable designware for rk3399Jagan Teki2020-04-301-0/+1
| | | | | | | | | | | | | | | | Enable designware watchdog driver for rk3399 if WDT defined. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256Jagan Teki2020-04-301-1/+2
| | | | | | | | | | | | | | | | IS25WP256 flash chips do support 4byte address opcodes, so enable support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com>
| * mtd: spi-nor: Enable QE bit for ISSI flashJagan Teki2020-04-301-0/+1
| | | | | | | | | | | | | | | | | | | | Enable QE bit for ISSI flash chips. QE enablement logic is similar to what Macronix has, so reuse the existing code itself. Cc: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: sifive: Tidy up dm_spi_slave_platdata variableJagan Teki2020-04-301-15/+15
| | | | | | | | | | | | | | | | | | | | | | Usually variable name slave is used for spi_slave structure and slave_plat for the dm_spi_slave_platdata. Let's follow this meaningful notation by replacing slave with slave_plat for dm_spi_slave_platdata structure. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * spi: spi-mem: Add SPI_MEM_NO_DATA to the spi_mem_data_dir enumTudor Ambarus2020-04-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit: 0ebb261a0b2d ("spi: spi-mem: Add SPI_MEM_NO_DATA to the spi_mem_data_dir enum") in linux. When defining spi_mem_op templates we don't necessarily know the size that will be passed when the template is actually used, and basing the supports_op() check on op->data.nbytes to know whether there will be data transferred for a specific operation is not possible. Add SPI_MEM_NO_DATA to the spi_mem_data_dir enum so that we can base our checks on op->data.dir instead of op->data.nbytes. This also fixes a bug identified with the atmel-quaspi driver. The spi-nor core, when erasing sectors, fills the spi_mem_op template using SPI_MEM_OP_NO_DATA, which initializes all the data members with value zero. This is wrong because data.dir is treated as SPI_MEM_DATA_IN, which translates in our driver to read accesses for erases (RICR), while the controller expects write accesses (WICR). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: nand: spi: add support for Toshiba TC58CVG2S0HRAIJRobert Marko2020-04-291-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Toshiba recently launched new revisions of their serial SLC NAND series. TC58CVG2S0HRAIJ is a refresh of previous series with minor improvements. Basic parameters are same so lets add support for this new revision. Datasheet: https://business.kioxia.com/info/docget.jsp?did=58601&prodName=TC58CVG2S0HRAIJ Signed-off-by: Robert Marko <robert.marko@sartura.hr> Tested-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi-nand: Import Toshiba SPI-NAND supportRobert Marko2020-04-293-1/+193
| | | | | | | | | | | | | | | | | | Linux has good support for Toshiba SPI-NAND, so lets import it. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Tested-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi-nor: Enable dual and quad read for s25fl256s0Bacem Daassi2020-04-291-1/+1
| | | | | | | | | | | | | | | | | | | | The s25fl256s0 supports dual and quad read like s25fl256s1. Enable it by adding SPI_NOR_DUAL_READ and SPI_NOR_QUAD_READ flags to the flash_info entry. Tested on real silicon and confirmed to be working. Signed-off-by: Bacem Daassi <Bacem.Daassi@cypress.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi-nor-ids: Enable SPI_NOR_OCTAL_READ flag for mt35xu*Kuldeep Singh2020-04-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 658df8bd9464 ("mtd: spi-nor-core: Add octal mode support") enables octal mode(1-1-8) support in spi-nor framework. mt35xu512aba and mt35xu02g supports SINGLE and OCTAL I/O. Hence, enable SPI_NOR_OCTAL_READ flag for these flashes. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: cadence-qspi: Move ref clock calculation to probePratyush Yadav2020-04-291-16/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "assigned-clock-parents" and "assigned-clock-rates" DT properties take effect only after ofdata_to_platdata() when clk_set_defaults() is called in device_probe(). Therefore clk get rate() would return a wrong value in ofdata_to_platdata() when compared with probe. Hence it needs to be moved to probe. Tested on u-boot-ti/next. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: use is_power_of_2 instead of hweight32 in spi_nor_write()Rasmus Villemoes2020-04-291-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | hweight32 is a somewhat expensive way to check for power-of-2. Use the is_power_of_2 helper, which does the standard and cheap idiom foo&(foo-1)==0. add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-96 (-96) Function old new delta spi_nor_write 388 292 -96 Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: Transform the FSL QuadSPI driver to use the SPI MEM APIKuldeep Singh2020-04-292-1114/+608
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support the SPI MEM API, instead of modifying the existing U-Boot driver, this patch adds a port of the existing Linux driver. This also has the advantage that porting changes and fixes from Linux will be easier. Porting of driver left most of the functions unchanged while few of the changes are: -Remove lock(mutexes) and irq handler as u-boot is a single core execution. -Remove invalid masterid as it was required specially for multicore execution in LS2088ARDB which is not the case in u-boot. -Remove clock support as changing spi speed is not supported in uboot and nor in linux. Currently tested on LS1088ARDB, LS1012ARDB, LS1046ARDB, LS1046AFRWY, LS1043AQDS, LS1021ATWR, LS2088ARDB, I.MX6ULL EVK. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini2020-04-302-2/+64
|\ \ | | | | | | | | | | | | - DM ACPI support (Part A) - Improve support for chain-loading x86 U-Boot
| * | pci: Avoid auto-config when chain loadingSimon Glass2020-04-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | When U-Boot is not the first-stage bootloader we don't want to re-configure the PCI devices, since this has already been done. Add a check to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | acpi: Add a method to write tables for a deviceSimon Glass2020-04-301-0/+62
| |/ | | | | | | | | | | | | | | A device may want to write out ACPI tables to describe itself to Linux. Add a method to permit this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
* | Merge tag 'xilinx-for-v2020.07-rc2' of ↵Tom Rini2020-04-304-13/+12
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2020.07-rc2 mmc: - Fix dt property handling via generic function clk: - Fix versal watchdog clock setting nand: - Fix zynq nand command comparison xilinx: - Enable ubifs - Sync board_late_init configurations with initrd_high setup - Make custom distro boot more verbose zynq: - Kconfig alignments - Fix nand cse configuration zynqmp: - Fix zcu104 low level qspi configuration - Small DT updates Signed-off-by: Tom Rini <trini@konsulko.com>
| * | ARM: zynq: Fix invalid check on NAND_CMD_NONE.Patrick van Gelder2020-04-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The end_cmd field in the variables cmd_phase_addr and data_phase_addr contains the value 0xFF when the end_cmd equals NAND_CMD_NONE. This should be 0x00. This is caused by comparing NAND_CMD_NONE (int) with end_cmd (u8). end_cmd will be promoted by the int value -1 and therefore is not equal to 0xFF. Solved by casting NAND_CMD_NONE to u8 which will avoid int promotion. Signed-off-by: Patrick van Gelder <patrick.vangelder@nl.bosch.com> Reviewed-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | clk: versal: Fix watchdog clock issueT Karthik Reddy2020-04-271-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable mux based clocks to populate LPD_LSBUS clock to xilinx_wwdt driver. Skip reading clock rate for the mux based clocks with parent clock id is zero. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
| * | mmc: zynq: parse dt when probingBenedikt Grassl2020-04-272-11/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the entry "bus-width = <8>" in the ZynqMP's sdhci nodes is not evaluated. This results in the bus width staying at its default value (4 bit in HS200 mode). Fix this by calling mmc_of_parse. This function also checks for the "no-1-8-v" and "max-frequency" entries. Remove the handling of those nodes from this driver. Signed-off-by: Benedikt Grassl <Benedikt.Grassl@rohde-schwarz.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2020-04-3012-93/+1025
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | - Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb, ls1043ardb, lx2160ardb, ls2088ardb, ls1088ardb. - Add GICv3 support for ls1028a, ls2088a, ls1088a. - Add lpuart support on ls1028aqds. - Few bug fixes and updates on ls2088a, ls1012a, ls1046a, ls1021a based platforms.
| * | driver: net: fm: add DM ETH supportMadalin Bucur2020-04-295-10/+447
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | driver: net: fm: add DM MDIO supportMadalin Bucur2020-04-291-2/+137
| | | | | | | | | | | | | | | | | | | | | Allow the MDIO devices to be probed based on the device tree. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | driver: net: fm: separate receive buffer free codeMadalin Bucur2020-04-291-26/+37
| | | | | | | | | | | | | | | | | | | | | Move the receive buffer free code in a separate function. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | driver: net: fm: change init_phy() paramMadalin Bucur2020-04-291-11/+8
| | | | | | | | | | | | | | | | | | | | | Change the init_phy() parameter to simplify the code. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | drivers: net: fsl-mc: add support for CONFIG_DM_ETHIoana Ciornei2020-04-291-12/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make any adjustments necessary in order to support DPAA2 devices probed using CONFIG_DM_ETH. While at it, fixup some styling issues aroung the switch-case statement. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | drivers: net: ldpaa: add DTS based probing supportIoana Ciornei2020-04-292-32/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_DM_ETH is enabled DPAA2 network interfaces will now probe based on DTS nodes with the "fsl,qoriq-mc-dpmac" compatible. In this case, transform the ldpaa_eth driver into a UCLASS_ETH driver and reuse the _open()/_tx()/_stop() functions already inplemented. For the moment, the ldpaa_eth driver will support both configurations: with or without CONFIG_DM_ETH enabled. Any 'struct eth_device' occurrence now has a matching 'struct udevice' made mutually exclusive based on the state of CONFIG_DM_ETH. Signed-off-by: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | drivers: net: add Layerscape mEMAC MDIO driverIoana Ciornei2020-04-293-0/+154
| | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the MDIO interface integrated in the mEMAC (Multi-rate Ethernet Media Access Controller) and the Fman 10G Ethernet MACs. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | | Merge tag 'u-boot-amlogic-20200428' of ↵Tom Rini2020-04-285-0/+262
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - fix sd-emmc controller A init on G12A/G12B/SM1 SoCs - add GXBB USB PHY driver - enable access to SPI NOR Flash on VIM2 and VIM3/VIM3L boards - fix USB PHYs Power-Up on on VIM3/VIM3L boards
| * | | usb: dwc3-meson-g12a: add power-on/off of the PHYsNeil Armstrong2020-04-281-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Power on/off the PHYs to enable power to the USB ports, fixing USB support on Khadas VIM3/VIM3L boards. The G12A USB complex has at least 2 USB2 PHYs, but one is muxed between the DWC2 and DWC3 controller and the other one directly connected to the DWC3 controller. The USB3+PCIe combo PHY is muxed between the DWC3 controller and a DW-PCIE controller. All PHYs are optional, but it's type (usb2/usb3) and position are important to determine it's capabilities, thus they are stored in a fixed size array and the phy-name determines it's position, it's position determining it's type and functionnalities. This is why we need to loop over the array to power on all the DT provided PHYs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | | phy: meson: add GXBB PHY driverBeniamino Galvani2020-04-283-0/+244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the USB PHY found on Amlogic GXBB SoCs. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | | clk: meson: g12a: add missing SD_EMMC_A controller gatesNeil Armstrong2020-04-281-0/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | Add missing SD_EMMC_A controller gates needed for probe of the A controller, otherwise leading to a freeze of the SoC after b3d69aa596. Fixes: b3d69aa596 ("clk: meson: reset mmc clock on probe") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2020-04-284-10/+104
|\ \ \ | | | | | | | | | | | | | | | | - DWC2/DWC3 improvements - Assorted bugfixes
| * | | usb: host: dwc3-sti-glue: Use UCLASS_NOP instead of UCLASS_MISCPatrice Chotard2020-04-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dwc3-sti-glue has been broken since MISC uclass has been modified to scan DT sub-nodes after bind. Fixing it by a using the no-op uclass. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| * | | usb: host: dwc2: add trace to have clean usb startPatrick Delaunay2020-04-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Solve issue for the display of "usb start" command on stm32mp1 because one carriage return is missing in DWC2 probe. Before the patch: STM32MP> usb start starting USB... Bus usb-otg@49000000: Bus usbh-ehci@5800d000: USB EHCI 1.00 after the patch: STM32MP> usb start starting USB... Bus usb-otg@49000000: USB DWC2 Bus usbh-ehci@5800d000: USB EHCI 1.00 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | usb: host: dwc2: force reset assertPatrick Delaunay2020-04-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Assert reset before deassert in dwc2_reset; this patch solve issues when the DWC2 registers are already initialized with value incompatible with host mode. Force a hardware reset of the IP reset all the DWC2 registers at default value, the host driver start with a clean state (Core Soft reset doen in dwc_otg_core_reset is not enought to reset all register). The error can occurs in U-Boot when DWC2 device gadget driver force device mode (called by ums or dfu command, before to execute the usb start command). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | usb: host: dwc2: add clk supportPatrick Delaunay2020-04-281-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for clock with driver model. This patch don't added dependency because when CONFIG_CLK is not activated the clk function are stubbed. Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | usb: host: dwc2: add phy supportPatrick Delaunay2020-04-281-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use generic phy to initialize the PHY associated to the DWC2 device and available in the device tree. This patch don't added dependency because when CONFIG_PHY is not activated, the generic PHY function are stubbed. Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | usb: ether: avoid NULL check before free()Heinrich Schuchardt2020-04-281-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | free() checks if its argument is NULL. Do not duplicate this check. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | | usb: avoid NULL check before freeHeinrich Schuchardt2020-04-281-6/+3
| |/ / | | | | | | | | | | | | | | | | | | The free() function checks if the argument is NULL. Do not duplicate this check. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | Merge tag 'mips-pull-2020-04-27' of ↵Tom Rini2020-04-274-1/+63
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mips - brcmnand: fix missing code path from Linux driver - bmips: fix build error when disabling USB - mips: add option to restore original exception vector base - mips: fix off-by-one error when clearing gd_data - mips: minor fixes for compatibility with generic SPL framework - spl: refactor legacy image loading - spl: add LZMA decompression support for legacy images - Makefile: add target to build LZMA compressed U-Boot images - mtmips: refactor and rewrite low-level init code - mtmips: add and enable SPL support with LZMA - mtmips: add support for MT7628 reference board - mtmips: add support for VoCore/VoCore2 board
| * | | sysreset: add reset controller based reboot driverWeijie Gao2020-04-273-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some chips provide their sysreset function in reset controller, which is normally a bit written to 1 to perform the sysreset. This patch adds a new sysreset driver to take advantage of it. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | | nand: brcmnand: return without disabling clockÁlvaro Fernández Rojas2020-04-271-1/+8
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Linux Broadcom NAND driver only disabled clock if no childs are initialized. This section of the code seems to have been accidentally dropped when it was imported in U-Boot. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
View Lorry Controller Status