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* net: Add SMC911X driver to Kconfig, convertAdam Ford2017-10-201-0/+28
| | | | | | | | | | | | | We add the various SMC91XX symbols to drivers/net/Kconfig and then this converts the following to Kconfig: CONFIG_SMC911X CONFIG_SMC911X_BASE CONFIG_SMC911X_16_BIT CONFIG_SMC911X_32_BIT Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Apply to the rest of the tree, re-squash old and new patch] Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_NAND_OMAP_GPMC et al and CONFIG_NAND_MXC to KconfigAdam Ford2017-10-201-1/+54
| | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_NAND_MXC CONFIG_NAND_OMAP_GPMC CONFIG_NAND_OMAP_GPMC_PREFETCH CONFIG_NAND_OMAP_ELM CONFIG_SPL_NAND_AM33XX_BCH CONFIG_SPL_NAND_SIMPLE CONFIG_SYS_NAND_BUSWIDTH_16BIT Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> [trini: Finish migration of CONFIG_SPL_NAND_SIMPLE, fix some build issues, add CONFIG_NAND_MXC so we can do CONFIG_SYS_NAND_BUSWIDTH_16BIT] Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-i2cTom Rini2017-10-182-13/+6
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| * i2c: stm32f7_i2c: fix usage of useless local variablePatrice Chotard2017-10-171-8/+2
| | | | | | | | | | | | | | Remove useless local variable "s" and use directly function's parameter "output" Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| * i2c: stm32f7_i2c: fix data abortChristophe Kerello2017-10-171-10/+11
| | | | | | | | | | | | | | | | | | | | As "v" is a local variable in stm32_i2c_choose_solution() "v" has to be copied into "s" to avoid data abort in stm32_i2c_compute_timing(). Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| * i2c: remove DECLARE_GLOBAL_DATA_PTR from i2c-uclassMasahiro Yamada2017-10-171-2/+0
| | | | | | | | | | | | | | No global pointer is used in this file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | Merge git://git.denx.de/u-boot-spiTom Rini2017-10-182-7/+65
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| * sf: bar: Clean BA24 Bank Address Register bit after read/write/erase operationLukasz Majewski2017-09-271-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The content of Bank Address Register (BAR) is volatile. It is cleared after power cycle or reset command (RESET F0h). Some memories (like e.g. s25fl256s) use it to access memory larger than 0x1000000 (16 MiB). The problem shows up when one: 1. Reads/writes/erases memory > 16 MiB 2. Calls "reset" u-boot command (which is not causing BAR to be cleared) In the above scenario, the SoC ROM sends 0x000000 address to read SPL. Unfortunately, the BA24 bit is still set and hence it receives content from 0x1000000 (16 MiB) memory address. As a result the SoC aborts and we hang. Only power cycle can take the SoC out of this state. How to reproduce/test: sf probe; sf erase 0x1200000 0x800000; reset sf probe; sf erase 0x1200000 0x800000; sf write 0x11000000 0x1200000 0x800000; reset sf probe; sf read 0x11000000 0x1200000 0x800000; reset Signed-off-by: Lukasz Majewski <lukma@denx.de> [Fixed comment text on clean_bar function] Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * SPL: SPI: sunxi: add SPL FIT image supportAndre Przywara2017-09-271-7/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | The sunxi-specific SPI load routine only knows how to load a legacy U-Boot image. Teach it how to handle FIT images as well, simply by providing the existing SPL FIT loader with the right loader routine to access the SPI NOR flash. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reported-by: Peter Kosa <kope@madnet.sk> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | usbtty: fix typosHeinrich Schuchardt2017-10-161-1/+1
| | | | | | | | | | | | Fix typos in USB tty driver. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | Drop CONFIG_HAS_DATAFLASHTuomas Tynkkynen2017-10-163-995/+0
| | | | | | | | | | | | | | | | Last user of this option went away in commit: fdc7718999 ("board: usb_a9263: Update to support DT and DM") Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
* | spi: Drop CONFIG_ATMEL_DATAFLASH_SPITuomas Tynkkynen2017-10-162-185/+0
| | | | | | | | | | | | | | | | | | Last user of this option went away in commit: fdc7718999 ("board: usb_a9263: Update to support DT and DM") Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
* | mmc: stm32_sdmmc2: increase polling status register delayChristophe Kerello2017-10-161-1/+1
| | | | | | | | | | | | | | | | | | MMC commands like MMC_CMD_ALL_SEND_CID or MMC_CMD_SEND_CSD can reach 500 us. This patch increases the polling status register delay to avoid a timeout on a command. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | dm: clk: fix PWR_CR3 register's bit 2 namePatrice Chotard2017-10-161-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix bit 2 name of PWR_CR3 register to match with the last STM32H7 reference manual available here : http://www.st.com/content/st_com/en/support/resources/ resource-selector.html?querycriteria=productId=SS1951$$ resourceCategory=technical_literature$$resourceType=reference_manual Update also comment about voltage scaling 1 values Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
* | dm: clk: remove CLK() macro for clk_stm32h7Patrice Chotard2017-10-161-115/+108
| | | | | | | | | | | | | | | | CLK() macro is a residue of a previously reworked patch, remove it. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
* | clk: uniphier: add NAND controller clockMasahiro Yamada2017-10-151-0/+12
| | | | | | | | | | | | This allows the NAND driver to enable clock and get its clock rate. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | mtd: nand: denali_dt: add clock supportMasahiro Yamada2017-10-152-0/+13
| | | | | | | | | | | | | | Enable clock in the probe hook. The clock rate will be necessary when setup_data_interface hook is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | reset: uniphier: fix the first argument passed to dev_err()Masahiro Yamada2017-10-151-1/+2
| | | | | | | | | | | | priv->dev does not exist. Pass the correct pointer to udevice. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | clk: uniphier: add PXs3 clock dataMasahiro Yamada2017-10-153-0/+23
| | | | | | | | | | | | Add basic clock data for Socionext's new SoC PXs3. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | clk: uniphier: rework for better clock tree structureMasahiro Yamada2017-10-154-183/+323
| | | | | | | | | | | | | | | | U-Boot does not support fancy clock tree structures like the Linux common clock framework. Implement a simple clock tree model at the driver level. With this, the clock data will be simplified. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | i2c: uniphier-f: replace debug() with dev_dbg()Masahiro Yamada2017-10-151-62/+52
| | | | | | | | | | | | | | | | | | | | Use dev_dbg() functions. It will be helpful to prefix log messages with the corresponding device name when the core framework is ready. While I am here, I renamed "dev", which was actually private data, into "priv" because dev->dev looks confusing. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | i2c: uniphier: replace debug() with dev_dbg()Masahiro Yamada2017-10-151-30/+33
| | | | | | | | | | | | | | | | | | | | Use dev_dbg() functions. It will be helpful to prefix log messages with the corresponding device name when the core framework is ready. While I am here, I renamed "dev", which was actually private data, into "priv" because dev->dev looks confusing. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | usb: dwc3-uniphier: replace <common.h> with <linux/bitops.h>Masahiro Yamada2017-10-151-1/+1
| | | | | | | | | | | | | | | | Including <common.h> pulls in a lot of bloat. What this driver needs is BIT(), so replace it with <linux/bitops.h> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Marek Vasut <marex@denx.de>
* | pinctrl: uniphier: simplify input enable and delete pin arraysMasahiro Yamada2017-10-156-89/+3
| | | | | | | | | | | | | | | | | | The pin data are implemented for old SoCs to specify the bit shift of the IECTRL register. They are not wortwhile given the required memory footprint. Delete all the pin data and enable all bits of the IECTRL register. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | pinctrl: uniphier: set PUPD_SIMPLE cap flag for PXs3Masahiro Yamada2017-10-151-1/+2
| | | | | | | | | | | | | | Like other recenct UniPhier SoCs, the pupdctrl number of PXs3 matches to the pin number. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | gpio: uniphier: rework single device node modelMasahiro Yamada2017-10-151-51/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First, I implemented this driver as per-bank model, but it was a design mistake. - There are 31 banks in the maximum case. It is painful to add so many nodes to DT. - The IRQ control registers are shared between banks. Per-bank design is a problem for Linux. The counterpart for Linux turned around to the single node model. Rework based on the driver for Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | mtd: nand: do not check R/B# for CMD_SET_FEATURES in nand_command(_lp)Masahiro Yamada2017-10-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set Features (0xEF) command toggles the R/B# pin after 4 sub feature parameters are written. Currently, nand_command(_lp) calls chip->dev_ready immediately after the address cycle because NAND_CMD_SET_FEATURES falls into default: label. No wait is needed at this point. If you see nand_onfi_set_features(), R/B# is already cared by the chip->waitfunc call. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [ Linux commit: c5d664aa5a4c4b257a54eb35045031630d105f49 ]
* | mtd: nand: do not check R/B# for CMD_READID in nand_command(_lp)Masahiro Yamada2017-10-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | Read ID (0x90) command does not toggle the R/B# pin. Without this patch, NAND_CMD_READID falls into the default: label, then R/B# is checked by chip->dev_ready(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [ Linux commit: 3158fa0e739615769cc047d2428f30f4c3b6640e ]
* | drivers: pci: imx: fix imx_pcie_remove functionSven-Ola Tuecke2017-10-121-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have at least a minor count of boards, that failed to re-initialize PCI express in the Linux kernel. Typical failure rate is 20% on affected boards. This is mitigated by commit 6ecbe1375671 ("drivers: pci: imx: add imx_pcie_remove function"). However, at least on some i.MX6 custom boards, when calling assert_core_reset() as part of the first-time PCIe init, read access to PCIE_PL_PFLR simply hangs. Surround this readl() with imx_pcie_fix_dabt_handler() does not help. For this reason, the forced LTSSM detection is only used on the second assert_core_reset() that is called shorly before starting the Linux kernel. Signed-off-by: Sven-Ola Tuecke <sven-ola.tuecke@numberfour.eu> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: David Müller <d.mueller@elsoft.ch>
* | Merge git://git.denx.de/u-boot-i2cTom Rini2017-10-111-1/+6
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| * | i2c: muxes: pca954x: look up width from chip_descChris Packham2017-10-111-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 8e6eda7cda6c ("drivers/i2c/muxes/pca954x: Add pca9547 I2C mux support") introduced a chip_desc for the pca954x devices but failed to update pca954x_ofdata_to_platdata() to be aware of it. Make pca954x_ofdata_to_platdata() lookup the chip_desc to validate the device width. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Marek Behun <marek.behun@nic.cz>
* | | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2017-10-1017-119/+12261
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| * | pinctrl: rmobile: Add pinconf to Renesas RCar pincontrol driverMarek Vasut2017-10-041-0/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinconf support to the PFC driver, so that it can handle DT props bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | usb: Drop the EHCI RCar Gen3Marek Vasut2017-10-043-115/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we use EHCI generic driver on RCar Gen3 , this driver is useless. Remove it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | gpio: rmobile: Add Renesas RCar GPIO driverMarek Vasut2017-09-283-0/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add GPIO driver for the Renesas RCar SoCs . The driver currently supports only the RCar Gen3 R8A7795 and R8A7796 SoCs, but is easily extensible for the other RCar SoCs as well. This driver is meant to replace the pinmux part of SH_GPIO_PFC driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | pinctrl: rmobile: Add Renesas RCar pincontrol driverMarek Vasut2017-09-288-0/+11802
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PFC pincontrol driver for the Renesas RCar Gen3 R8A7795 and R8A7796 SoCs. This driver uses the PFC pin tables from Linux, thus letting us share the occassional fixes to those tables. This driver also has a DT support, so the pinmux is configured from DT instead of the ad-hoc setup in board file. This driver is meant to replace the pinmux part of SH_GPIO_PFC driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | serial: sh: Enable clock if availableMarek Vasut2017-09-241-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the clock framework provides the driver with valid clock, enable them, otherwise the SCIF might not work if the clock are not enabled prior to the driver probe. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | net: ravb: Add PHY reset GPIO supportMarek Vasut2017-09-241-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for obtaining PHY reset GPIO from DT and toggling it before configuring the PHY to put the PHY into defined state. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | clk: rmobile: Add RPC hyperflash clockMarek Vasut2017-09-241-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | Add missing RPC hyperflash entry into the clock driver tables. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | clk: rmobile: Add support for setting SDxCKCRMarek Vasut2017-09-241-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SDxCKCR must be configured correctly, otherwise the SDIF can be unstable. This is done in board files thus far, but those are going away, so move the setting of SDxCKCR into the correct place. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | Merge git://git.denx.de/u-boot-dmTom Rini2017-10-0913-51/+44
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| * | | dm: ofnode: query correct property in livetree ofnode_get_addr_sizeKlaus Goger2017-10-081-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The livetree codepath of ofnode_get_addr_size always used the "reg" property for of_get_property. Use the property parameter of the function call instead and check the return value if the property exists. Otherwise return FDT_ADDR_T_NONE. This was discoverd while using SPI NOR with livetree. spi_flash_decode_fdt checks for memory-map and will not fail with livetree even if the property does not exist. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Round up size when allocating so that it is cache line alignedFaiz Abbas2017-10-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The size variable may not be always be a mulitple of ARCH_DMA_MINALIGN and using it to flush cache leads to cache misaligned warnings. Therefore, round up the size to a multiple of ARCH_DMA_MINLAIGN when allocating private data. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | dm: gpio: pca953x: Drop pointless data structure checksSimon Glass2017-10-081-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These checks cannot fail since driver model will not call a driver's method if it cannot fully create the driver data structures. It is confusing to have these checks and others might copy them. Drop this code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dm: gpio: Correct use of -ENODEV in driversSimon Glass2017-10-089-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In U-Boot -ENODEV means that there is no device. When there is a problem with the device, drivers should return an error like -ENXIO or -EREMOTEIO. When the device tree properties cannot be read correct , they should return -EINVAL. Update various GPIO drivers to follow this rule, to help with consistency for future driver writers. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Adam Ford <aford173@gmail.com>
| * | | dm: gpio: Add a comment about not copying some driversSimon Glass2017-10-083-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These three drivers all use U_BOOT_DEVICE rather than device tree to create devices, so have to do manual allocation of platform data. This is not true for new platforms. Add a more explicit comment so that people do not copy this approach with new boards. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Adam Ford <aford173@gmail.com>
| * | | dm: gpio: vybrid_gpio: Correct driver's use of bind() methodSimon Glass2017-10-081-19/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It does not look like this driver needs to use a bind() method. It does not manually create devices with device_bind() nor does it create devices using U_BOOT_DEVICE(). It seems to only use device tree. Therefore the manual allocation of platform data is not needed and is confusing. Also platform data should be set up by the ofdata_to_platdata() method, not bind(). Update the driver in case others use it as a model in future. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Adam Ford <aford173@gmail.com>
* | | | Merge git://git.denx.de/u-boot-videoTom Rini2017-10-093-3/+214
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| * | | | dm: video: Add color ANSI escape sequence supportRob Clark2017-09-291-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Note that this doesn't differentiate (due to lack of information in video_priv) between different possible component orders for 32bpp. But the main user at this point is efi_loader, and GOP expects xBGR so any video drivers that this is incorrect for already have problems. (Also, conveniently, this matches what simple-framebuffer bindings expect for kernels that use the simple-framebuffer DT binding to take over the bootloader display.) Signed-off-by: Rob Clark <robdclark@gmail.com>
| * | | | dm: video: Add basic ANSI escape sequence supportRob Clark2017-09-293-3/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Really just the subset that is needed by efi_console. Perhaps more will be added later, for example color support would be useful to implement efi_cout_set_attribute(). Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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