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* Merge tag 'efi-2020-04-rc1' of ↵WIP/08Jan2020Tom Rini2020-01-0812-0/+369
|\ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-04-rc1 This pull request provides: * support for FIT images for UEFI binaries * drivers for hardware random number generators * an implementation of the EFI_RNG_PROTOCOL * a sub-command for efidebug to display configuration tables
| * virtio: rng: Add a random number generator(rng) driverSughosh Ganu2020-01-074-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the virtio-rng device on the qemu platform. The device uses pci as a transport medium. The driver can be enabled with the following configs CONFIG_VIRTIO CONFIG_DM_RNG CONFIG_VIRTIO_PCI CONFIG_VIRTIO_RNG Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
| * sandbox: rng: Add a random number generator(rng) driverSughosh Ganu2020-01-073-0/+65
| | | | | | | | | | | | | | | | | | Add a sandbox driver for random number generation. Mostly aimed at providing a unit test for rng uclass. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * stm32mp1: rng: Add a driver for random number generator(rng) deviceSughosh Ganu2020-01-073-0/+168
| | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the rng device found on stm32mp1 platforms. The driver provides a routine for reading the random number seed from the hardware device. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com> Remove a superfluous blank line Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * clk: stm32mp1: Add a clock entry for RNG1 deviceSughosh Ganu2020-01-071-0/+1
| | | | | | | | | | | | | | | | | | Add an entry for allowing clock enablement for the random number generator peripheral, RNG1. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
| * dm: rng: Add random number generator(rng) uclassSughosh Ganu2020-01-075-0/+39
| | | | | | | | | | | | | | | | | | | | Add a uclass for reading a random number seed from a random number generator device. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge tag 'u-boot-imx-20200108' of ↵Tom Rini2020-01-0811-0/+560
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx --------------------------------------------------------------------- Add i.MX8MP SoC and EVK board Update README for i.MX8MN EVK and fix mmc env Add pca9450 driver -------------------------------------------------------------------- Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/634211885
| * | clk: imx: add i.MX8MP clk driverPeng Fan2020-01-083-0/+380
| | | | | | | | | | | | | | | | | | Add i.MX8MP clk driver for i.MX8MP CLK driver model usage Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | clk: imx: add imx_clk_mux2_flagsPeng Fan2020-01-081-0/+10
| | | | | | | | | | | | | | | | | | Add imx_clk_mux2_flags which will be used by i.MX8MP Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | power: Add new PMIC PCA9450 driverYe Li2020-01-084-0/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | PCA9450 PMIC series is used to support iMX8MM (PCA9450A) and iMX8MN (PCA9450B). Add the PMIC driver for both PCA9450A and PCA9450B. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | ddr: imx8m: Add DRAM PLL to generate 1000Mhz outputPeng Fan2020-01-081-0/+4
| | | | | | | | | | | | | | | | | | | | | We will generate DRAM 4000MT/s as default for i.MX8MP. So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | mxc_ocotp: support i.MX8MPPeng Fan2020-01-081-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | i.MX8MP use similar ocotp as i.MX8MN, but has changed fuse banks and ctrl register bit definitions, so update to reflect that. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | pinctrl: imx8m: support i.MX8MPPeng Fan2020-01-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add i.MX8MP compatible to let the pinctrl driver could support i.MX8MP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2020-01-0819-481/+1695
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| * | | ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC AccessThor Thayer2020-01-072-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ECC registers in the SDRAM HMC Adapter should always be accessible (both when ECC is enabled and disabled). Currently, the registers are accessible only when ECC is enabled. The ECC Enabled bit is used to determine the status of ECC by later OSes so always allow access. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | arm: socfpga: stratix10: Enable SMMU accessThor Thayer2020-01-071-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable TCU access through the Stratix10 CCU so that the SMMU can access the SDRAM. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | ddr: altera: agilex: Add SDRAM driver for AgilexLey Foon Tan2020-01-075-3/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SDRAM driver for Agilex SoC. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | | ddr: altera: Restructure Stratix 10 SDRAM driverLey Foon Tan2020-01-075-443/+493
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Restructure Stratix 10 SDRAM driver. Move common code to separate file, in preparation to support SDRAM driver for Agilex. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | | cache: Add Arteris Ncore cache coherent unit driverLey Foon Tan2020-01-073-0/+173
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Cache Coherency Unit (CCU) driver. CCU is to ensures consistency of shared data between multi masters in the system. Driver initializes CCU's directories and coherency agent interfaces in CCU IP. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | | clk: agilex: Add clock driver for AgilexLey Foon Tan2020-01-073-0/+817
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock manager driver for Agilex. Provides clock initialization and get_rate functions. agilex-clock.h is from Linux commit ID cd2e1ad12247. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | | arm: socfpga: Move Stratix10 and Agilex system manager common codeLey Foon Tan2020-01-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move Stratix10 and Agilex system manager common code to system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | | arm: socfpga: Move firewall code to firewall fileLey Foon Tan2020-01-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move firewall related code to new firewall.c, to share code in Stratix 10 and Agilex. SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC to allow DMA transfer to OCRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | | arm: socfpga: Convert clock manager from struct to definesLey Foon Tan2020-01-071-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get clock manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | | arm: socfpga: Convert system manager from struct to definesLey Foon Tan2020-01-075-22/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | | arm: socfpga: Convert reset manager from struct to definesLey Foon Tan2020-01-071-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get reset manager base address from DT node instead of using #define. spl_early_init() initializes the DT setup. So, move spl_early_init() to beginning of function and before get base address from DT. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | | spl: Allow cache drivers to be used in SPLLey Foon Tan2020-01-072-1/+2
| | |/ | |/| | | | | | | | | | | | | | | | | | | Add an option for building cache drivers in SPL. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* | | Merge tag 'u-boot-amlogic-20200108' of ↵Tom Rini2020-01-087-15/+39
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - Khadas VIM3L based on Amlogic S905D3 support - Various fixups for amlogic boards - Unnecessary header includes drop into video/meson
| * | | video: meson: Drop unnecessary header includesSimon Glass2020-01-077-15/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These files should not be included in meson header files. Drop them and tidy up the affected C files. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | | | ata: fsl_sata: Continue probing other sata port when failed current port.WIP/2020-01-07-master-importsPeng Ma2020-01-081-7/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the initialization of sata driver, we want to initialize all port probes, Therefore, any detection failure between of them should continue initialization by skipping the current port instead of exit. Signed-off-by: Peng Ma <peng.ma@nxp.com>
* | | | ata: sata_sil: Continue probing other sata port when failed current port.Peng Ma2020-01-081-4/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the initialization of sata driver, we want to initialize all port probes, Therefore, any detection failure between of them should continue initialization by skipping the current port instead of exit. Signed-off-by: Peng Ma <peng.ma@nxp.com>
* | | | power: regulator: support off-on-delay-usPeng Fan2020-01-071-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | off-on-delay-us has been supported by Linux, so let's use it. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | | | remoteproc: stm32: load resource table from firmwareFabien Dessenne2020-01-071-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Load the optional resource table from the firmware, and write its address in the dedicated backup register. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
* | | | remoteproc: stm32: track the coprocessor state in a backup registerFabien Dessenne2020-01-071-12/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the dedicated backup register to track the coprocessor state and rely on that register to compute the .is_running() value (which expects a return value of 0 -not 1- if the processor is running). Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
* | | | remoteproc: elf_loader: Add elf resource table load supportFabien Dessenne2020-01-071-0/+269
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add rproc_elf_load_rsc_table(), which searches for a resource table in an elf64/elf32 image, and if found, copies it to device memory. Add also the elf32 and elf64 variants of this API. Add a test for this. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | | drivers: board: Add get_fit_loadable()Jean-Jacques Hiblot2020-01-071-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function will be used by the SPL to get the names of images to load from the FIT. This allows to load different images based on runtime HW detection. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | drivers: board: Make the board drivers available in SPLJean-Jacques Hiblot2020-01-073-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the board driver available in the SPL too. The board driver is a way to provide useful information about the board and that can be useful in the SPL too. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | Merge tag 'u-boot-imx-20200107' of ↵WIP/07Jan2020Tom Rini2020-01-075-47/+157
|\ \ \ \ | | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx New for 2020.04 --------------- - New boards Embedded Artists COM board Xea Board - Switch to DM: Aristainetos boards Toradex colibri (DM_ETH) iCubox GE bx50v3 mx7dsabre (DM_ETH) cx9020 - New features: Bootaux with elf files Default SYS_THUMB_BUILD for i.MX6/7 - Fixes: DHCOM i.MX6 PDK Engicam i.MX8M tools (imx8m_image) Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
| * | | ddr: imx8m: Return error values from LPDDR4 trainingFrieder Schrempf2020-01-073-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In cases when the same SPL should run on boards with i.MX8MM, that differ in DDR configuration, it is necessary to try different parameters and check if the training done by the firmware suceeds or not. Therefore we return the DDR training/initialization success to the upper layer in order to be able to retry with different settings if necessary. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
| * | | pci: imx: Add iMX6SX compatibleMarek Vasut2020-01-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver works fine with iMX6SX, add the missing compatible string. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | video: lg4573: convert to DMHeiko Schocher2020-01-071-39/+136
| |/ / | | | | | | | | | | | | | | | convert this driver to support DM. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | Merge tag 'u-boot-atmel-2020.04-a' of ↵Tom Rini2020-01-071-2/+44
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel features for 2020.04 cycle This feature set is a patch series from Tudor Ambarus which includes parsing of the spi flash SFDP parser for SST flashes, and using those tables to retrieve unique saved per device MAC address. This is then used as base mac address on the SAMA5D2 Wireless SOM EK board.
| * | mtd: spi: spi-nor-core: Add SST vendor specific SFDP parserTudor Ambarus2019-12-171-2/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | JESD216 allow vendors to define their own SFDP tables. Add SST SFDP parser. The vendor table is allocated using resource-managed kmalloc - the table will be freed on driver detach. It will be accessible by getting the UCLASS_SPI_FLASH's private data. The SST's SFDP table is particularly of interest because contains pre-programmed globally unique EUI-48 and EUI-64 identifiers. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
* | | Merge branch 'next'WIP/06Jan2020Tom Rini2020-01-0678-408/+4034
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bring in the following merges: commit 8fbbec12f7d2c18f8883f3371cfca74a98b5dd87 Merge: 87f69f467a83 63618e71e89b Author: Tom Rini <trini@konsulko.com> Date: Fri Jan 3 09:48:47 2020 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next - updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support commit 87f69f467a8335b171c71bf217d2625d515acd7c Merge: c0912f9bbfb2 4466b9970319 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 24 08:18:19 2019 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next - Enable DM driver on ppc/km boards - Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x, T104x, P4080, P2041, P2020, P1020, P3041 - Some updates in mpc85xx-ddr driver, km boards commit c0912f9bbfb26dd03d189953678691b799d35b6e Merge: 533c9f5714bd a1d6dc3f8407 Author: Tom Rini <trini@konsulko.com> Date: Wed Dec 18 07:20:19 2019 -0500 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next - Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral commit 533c9f5714bdba79dc6f2629284d4c1a08a611d1 Merge: 553cb0688782 033e18b47bd0 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 17 07:53:08 2019 -0500 Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next i2c: for next - misc: i2c_eeprom: Add partition support and add ability to query size of eeprom device and partitions - i2c common: add support for offset overflow in to address and add sandbox tests for it. commit 553cb06887825314e74a9bdac337467c77d1db88 Merge: f39abbbc531e b4f98b3b16ec Author: Tom Rini <trini@konsulko.com> Date: Thu Dec 12 08:18:59 2019 -0500 Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next buildman improvements including toolchain environment feature sandbox unicode support in serial
| * | pci: layerscape: Manage PCIe EP compatible string via KconfigPankaj Bansal2020-01-023-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ep node device tree name is governed by these bindings: https://github.com/torvalds/linux/blob/master/Documentation/ devicetree/bindings/pci/layerscape-pci.txt#L24 As per above the ep compatible node contains platform name. Therefore, define the ep node compatible as CONFIG to find the pcie ep node in device tree during device tree fixup. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: layerscape: move PCIE related CONFIG to PCI KconfigPankaj Bansal2020-01-021-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | move the PCIE related config from arch Kconfig to PCI Kconfig. As the PCI_LAYERSCAPE driver is being used in platform other than fsl-layerscape platforms like ls102xa. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | armv8: lx2160a: Add FSL_PEX_STREAM_ID_END for LX2160AWasim Khan2019-12-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add FSL_PEX_STREAM_ID_END and remove FSL_PEX_STREAM_ID_NUM for lx2160a. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: layerscape_gen4: Suffix API names with _ls_gen4Wasim Khan2019-12-261-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update API names for layerscape gen4 fixup. Suffix layerscape_gen4 fixup API names with _ls_gen4. This is required to organize device tree fixup in common, layerscape and layerscape_gen4 specific code. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: layerscape: Suffix API names with _lsWasim Khan2019-12-261-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Suffix layerscape fixup API names with _ls. This is required to organize device tree fixup in common, layerscape and layerscape_gen4 specific code. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: layerscape: Add stream_id_cur field to ls_pcie structureWasim Khan2019-12-262-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add stream_id_cur field to ls_pcie structure and initialize it with 0 for all pcie controllers. This field will be used for streamId calculation. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | drivers/pci : enable pcie_layerscape code for lx2160a rev2Wasim Khan2019-12-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | lx2160a rev1 uses pcie_layerscape_gen4 driver and lx2160a rev2 uses pcie_layerscape driver. Enable pcie_layerscape code for CONFIG_PCIE_LAYERSCAPE_GEN4. Based on SoC and revision pcie controller probe will be invoked. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
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