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* dm: core: Set return value first in lists_bind_fdt()Simon Glass2017-06-011-2/+2
| | | | | | Adjust the order to make it clear that *devp is set to NULL by default. Signed-off-by: Simon Glass <sjg@chromium.org>
* tegra: Convert MMC to use driver model for operationsSimon Glass2017-06-011-31/+41
| | | | | | | Enable CONFIG_DM_MMC_OPS and CONFIG_BLK for all Tegra devices. This moves Tegra to use driver model fully for MMC. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: Rewrite mmc_blk_probe()Simon Glass2017-06-011-6/+11
| | | | | | | | | | | | | | This function is called when the MMC block device is being probed. There is a recursive call in this function since find_mmc_device() itself can cause the MMC device to be probed. Admittedly the MMC device should already be probed, since we would not be probing its child otherwise, but the current code is unnecessarily convoluted. Rewrite this to access the MMC structure directly. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: Check that drivers have operationsSimon Glass2017-06-011-0/+4
| | | | | | | | When binding a new MMC device, make sure that it has the required operations. Since for now we still support *not* having the operations (with CONFIG_DM_MMC_OPS not enabled) it makes sense to add this check. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: blk: Improve block device claimingSimon Glass2017-06-011-3/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The intention with block devices is that the device number (devnum field in its descriptor) matches the alias of its parent device. For example, with: aliases { mmc0 = "/sdhci@700b0600"; mmc1 = "/sdhci@700b0400"; } we expect that the block devices for mmc0 and mmc1 would have device numbers of 0 and 1 respectively. Unfortunately this does not currently always happen. If there is another MMC device earlier in the driver model data structures its block device will be created first. It will therefore get device number 0 and mmc0 will therefore miss out. In this case the MMC device will have sequence number 0 but its block device will not. To avoid this, allow a device to request a device number and bump any existing device number that is using it. This all happens during the binding phase so it is safe to change these numbers around. This allows device numbers to match the aliases in all circumstances. Add a test to verify the behaviour. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: blk: Add a function to find the next block device numberSimon Glass2017-06-011-6/+16
| | | | | | | At present this code is inline. Move it into a function to allow it to be used elsewhere. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: blk: Allow finding block devices without probingSimon Glass2017-06-011-2/+13
| | | | | | | Sometimes it is useful to be able to find a block device without also probing it. Add a function for this as well as the associated test. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: Don't call board_mmc_power_init() with driver modelSimon Glass2017-06-011-4/+11
| | | | | | | | We should not call out to board code from drivers. With driver model, mmc_power_init() already has code to use a named regulator, but the legacy code path remains. Update the code to make this clear. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Adjust device_bind_common() to take an ofnodeSimon Glass2017-06-011-8/+10
| | | | | | | This core function will need to work with a live tree also. Update it to accept an ofnode instead of an offset. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Add ofnode to represent device tree nodesSimon Glass2017-06-012-2/+2
| | | | | | | | | | With live tree we need a struct device_node * to reference a node. With the existing flat tree, we need an int offset. We need to unify these into a single value which can represent both. Add an ofnode union for this and adjust existing code to move to this. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Replace of_offset with accessor (part 2)Simon Glass2017-06-0122-33/+35
| | | | | | | | | At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Dont export dm_scan_fdt_node()Simon Glass2017-06-011-2/+15
| | | | | | | | This function is only used in one place. It is better to just declare it internally since there is a simpler replacement for use outside the driver-model core code. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Fix up inclusion of common.hSimon Glass2017-06-0122-2/+23
| | | | | | | | | | | | | | It is good practice to include common.h as the first header. This ensures that required features like the DECLARE_GLOBAL_DATA_PTR macro, configuration options and common types are available. Fix up some files which currently don't do this. This is necessary because driver model will soon start using global data and configuration in the dm/read.h header file, included via dm.h. The gd->fdt_blob value will be used to access the device tree and CONFIG options will be used to determine whether to support inline functions in the header file. Signed-off-by: Simon Glass <sjg@chromium.org>
* atmel: Fix up use of dm_scan_fdt_node()Simon Glass2017-06-011-2/+1
| | | | | | | This function should not be used outside the core driver-model code. Update it to use dm_scan_fdt_dev() instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Rename dev_addr..() functionsSimon Glass2017-06-01190-263/+265
| | | | | | | | | | | | | | | | | | | These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Move dev_get_addr() etc. into a separate fileSimon Glass2017-06-013-126/+144
| | | | | | | | Move this group of address-related functions into a new file. These use the flat device tree. Future work will provide new versions of these which can support the live tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Use dm.h header when driver mode is usedSimon Glass2017-06-0158-60/+58
| | | | | | | | This header includes things that are needed to make driver build. Adjust existing users to include that always, even if other dm/ includes are present Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2017-05-319-19/+303
|\ | | | | | | | | Please pull another update for Broadcom MIPS. This contains new SoC's, new boards and new drivers and some bugfixes.
| * dm: serial: bcm6345: fix baud rate clock calculationÁlvaro Fernández Rojas2017-05-311-4/+4
| | | | | | | | | | | | | | It's currently bugged and doesn't work for even cases. Right shift bits instead of dividing and fix even cases. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
| * dm: serial: bcm6345: fix uart stop bitsÁlvaro Fernández Rojas2017-05-311-0/+2
| | | | | | | | | | | | | | I missed this when I added support for BMIPS UART driver and it's needed to achieve a real 115200 8N1 setup. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
| * dm: cpu: bmips: add BCM6338 supportÁlvaro Fernández Rojas2017-05-311-0/+14
| | | | | | | | | | | | | | BCM6338 has a fixed CPU frequency of 240 MHz. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: cpu: bmips: add BCM3380 supportÁlvaro Fernández Rojas2017-05-311-0/+14
| | | | | | | | | | | | | | | | As far as I know BCM3380 has a fixed CPU frequency since I couldn't find its PLL registers in any documentation. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: ram: bmips: add BCM6338/BCM6348 supportÁlvaro Fernández Rojas2017-05-311-0/+31
| | | | | | | | | | Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: ram: bmips: split bcm6358_get_ram_sizeÁlvaro Fernández Rojas2017-05-311-10/+13
| | | | | | | | | | | | | | This is done in order to reuse ram size calculation for BCM6338/BCM6348 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: cpu: bmips: add BCM6348 supportÁlvaro Fernández Rojas2017-05-311-0/+34
| | | | | | | | | | Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: cpu: bmips: rename cpu_desc specific functionsÁlvaro Fernández Rojas2017-05-311-5/+5
| | | | | | | | | | | | | | Use a generic name for cpu_desc functions instead of using a specific SoC one. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: sysreset: add watchdog-reboot driverÁlvaro Fernández Rojas2017-05-313-0/+67
| | | | | | | | | | | | | | | | Add a new sysreset driver that uses the recently added watchdog support. It performs a full SoC reset by calling wdt_expire_now op. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: watchdog: add BCM6345 watchdog driverÁlvaro Fernández Rojas2017-05-313-0/+119
| | | | | | | | | | | | | | This driver is a simplified version of linux/drivers/watchdog/bcm63xx_wdt.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | pinctrl: mvebu: Enable support for the Armada 37xx pinctrl driverStefan Roese2017-05-313-6/+17
| | | | | | | | | | | | | | | | | | | | To enable support for the Armada 37xx pinctrl driver, we need to change the Kconfig symbol for the Armada 7k/8k pinctrl driver and its dependencies to distinguish between both platforms and drivers. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
* | pinctrl: armada-37xx: Add gpio supportGregory CLEMENT2017-05-311-0/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO management is pretty simple and is part of the same IP than the pin controller for the Armada 37xx SoCs. This patch adds the GPIO support to the pinctrl-armada-37xx.c file, it also allows sharing common functions between the gpio and the pinctrl drivers. Ported to U-Boot based on the Linux version by Stefan Roese. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
* | pinctrl: armada-37xx: Add pin controller support for Armada 37xxGregory CLEMENT2017-05-311-0/+469
|/ | | | | | | | | | | | | | | | | The Armada 37xx SoC come with 2 pin controllers: one on the south bridge (managing 28 pins) and one on the north bridge (managing 36 pins). At the hardware level the controller configure the pins by group and not pin by pin. This constraint is reflected in the design of the driver: only the group related functions are implemented. Ported to U-Boot based on the Linux version by Stefan Roese. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
* power: pmic: tps65218: Fix tps65218_voltage_update functionKeerthy2017-05-291-1/+1
| | | | | | | | | | | | | | Currently while setting the vsel value for dcdc1 and dcdc2 the driver is wrongly masking the entire 8 bits in the process clearing PFM (bit7) field as well. Hence describe an appropriate mask for vsel field and modify only those bits in the vsel mask. Source: http://www.ti.com/lit/ds/symlink/tps65218.pdf Signed-off-by: Keerthy <j-keerthy@ti.com> Fixes: 86db550b38 ("power: Add support for the TPS65218 PMIC") Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: meson: increase max block number per requestHeiner Kallweit2017-05-291-1/+1
| | | | | | | | Number of blocks is a 9 bit field where 0 stands for a unlimited number of blocks. Therefore the max number of blocks which can be set is 511. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
* drivers/power/regulator/max77686.c: Fix comparisons of unsigned expressionsTom Rini2017-05-291-8/+8
| | | | | | | | | | | | | | Inside of max77686_buck_volt2hex/max77686_buck_hex2volt/max77686_ldo_volt2hex we check that the value we calculate is >= 0 however we declare 'hex' as unsigned int making these always true. Mark these as 'int' instead. We also move hex_max to int as they are constants that are 0x3f/0xff. Given that the above functions are marked as returning an int, make the variables we assign their return value to also be int to be able to catch the error condition now. Reported by clang-3.8. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-05-265-12/+28
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| * armv8: ls2080ardb: Add LS2081ARDB board supportPriyanka Jain2017-05-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | LS2081ARDB board is similar to LS2080ARDB board with few differences It hosts LS2081A SoC Default boot source is QSPI-boot It does not have IFC interface RTC and QSPI flash device are different It provides QIXIS access via I2C Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC supportPriyanka Jain2017-05-233-4/+13
| | | | | | | | | | | | | | | | | | | | | | The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver: net: fsl-mc: Update fsl_mc_ldpaa_exit() pathYogesh Gaur2017-05-231-7/+13
| | | | | | | | | | | | | | | | | | | | | | Earlier when MC is loaded but DPL is not deployed results in FDT fix-up code execution hangs. For this case now print message on console and return success instead of return -ENODEV. This update allows fdt fixup to continue execution. Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Priyanka Jain <Priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-nds32Tom Rini2017-05-262-47/+228
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | Move FTMAC100 to where it should be, alphabetically in drivers/net/Kconfig Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: drivers/net/Kconfig
| * | nds32: eth: Support ftmac100 DM.rick2017-05-232-47/+228
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support Andestech eth ftmac100 device tree flow on AG101P/AE3XX platform. Verification: Boot linux kernel via dhcp and bootm ok. NDS32 # setenv bootm_size 0x2000000;setenv fdt_high 0x1f00000; NDS32 # dhcp 0x600000 10.0.4.97:boomimage-310y-ae300-spi.bin BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 BOOTP broadcast 4 DHCP client bound to address 10.0.4.178 (4899 ms) Using mac@e0100000 device TFTP from server 10.0.4.97; our IP address is 10.0.4.178 Filename 'boomimage-310y-ae300-spi.bin'. Load address: 0x600000 Loading: ################################################################# ################################################################# ################################################################# ... ... ################################### 233.4 KiB/s done Bytes transferred = 13872076 (d3abcc hex) NDS32 # dhcp 0x2000000 10.0.4.97:ae300.dtb BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 BOOTP broadcast 4 DHCP client bound to address 10.0.4.178 (4592 ms) Using mac@e0100000 device TFTP from server 10.0.4.97; our IP address is 10.0.4.178 Filename 'ae300.dtb'. Load address: 0x2000000 Loading: # 82 KiB/s done Bytes transferred = 2378 (94a hex) NDS32 # bootm 0x600000 - 0x2000000 Image Name: Created: 2017-03-22 6:52:03 UTC Image Type: NDS32 Linux Kernel Image (uncompressed) Data Size: 13872012 Bytes = 13.2 MiB Load Address: 0000c000 Entry Point: 0000c000 Verifying Checksum ... OK Booting using the fdt blob at 0x2000000 Loading Kernel Image ... OK Loading Device Tree to 01efc000, end 01eff949 ... OK Linux version 3.10.102-20375-gb0034c1-dirty (rick@app09) (gcc version 4.9.3 (2016-07-06_nds32le-linux-glibc-v3_experimental) ) #293 PREEMPT Wed Mar 22 14:49:28 CST 2017 CPU: NDS32 N13, AndesCore ID(wb), CPU_VER 0x0d11103f(id 13, rev 17, cfg 4159) ... ... Signed-off-by: rick <rick@andestech.com>
* | | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2017-05-235-7/+623
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| * | serial: sh: Add r8a7796 supportHiroyuki Yokoyama2017-05-221-1/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | net: ravb: Add Renesas Ethernet RAVB driverMarek Vasut2017-05-223-0/+610
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for the Renesas Ethernet AVB block found in RCar H3/M3. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Tom Rini <trini@konsulko.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Based on work of: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Takeshi Kihara <takeshi.kihara.df@renesas.com> Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
| * | gpio: rcar_gen3: Fix GPIO read supportKouei Abe2017-05-221-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes to read the GPIO status after confirming the INOUT setting. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2017-05-224-2/+119
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| * | | usb: ehci: Add Renesas RCar M3/H3 EHCI supportHiroyuki Yokoyama2017-05-223-0/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a USB controller driver for the EHCI block in R8A7795/R8A7796 SoC. This is a stopgap measure until we have proper DT support, clock and reset framework in place, at which point we can switch to ehci-generic. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | net: usb: mcs7830: fix non-DM ingress pathUri Mashiach2017-05-211-2/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | The mcs7830_recv() (non-DM) function discards good packets and tries to process "bad" packets due to incorrect test condition. Fix the condition and return the proper value as described in function doc. Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* | | Merge branch 'master' of git://git.denx.de/u-boot-nds32Tom Rini2017-05-224-0/+253
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| * | | nds32: Support AE3XX platform.rick2017-05-223-3/+127
| | | | | | | | | | | | | | | | | | | | | | | | Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com>
| * | | nds32: Support AG101P timer DM.rick2017-05-223-0/+129
| |/ / | | | | | | | | | | | | | | | Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com>
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