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* imx8: fuse: fix fuse driverMarcel Ziswiler2019-06-111-2/+0
| | | | | | | | This fixes the i.MX 8 fuse driver to actually build for i.MX 8QM as well. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
* clk: imx8qm: fix usdhc2 clocksMarcel Ziswiler2019-06-111-0/+18
| | | | | | | | | | | | | Trying to bring up uSDHC2 the following error message was observed: MMC: imx8_clk_set_rate(Invalid clk ID #60) imx8_clk_set_rate(Invalid clk ID #60) usdhc@5b030000 - probe failed: -22 This commit fixes this by properly setting resp. clocks. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
* spi: imx: work with cs greater 0Heiko Schocher2019-06-111-22/+52
| | | | | | | currently spi mxc driver can only handle cs 0. Allow it to handle also cs > 0. Signed-off-by: Heiko Schocher <hs@denx.de>
* spi: imx: remove doubled pointer from mxc_spi_probeHeiko Schocher2019-06-111-4/+3
| | | | | | | | | | | in mxc_spi_probe() plat and mxcs pointer are created: struct mxc_spi_slave *plat = bus->platdata; struct mxc_spi_slave *mxcs = dev_get_platdata(bus); which have the same value. Remove plat pointer. Signed-off-by: Heiko Schocher <hs@denx.de>
* Revert "drivers/crypto/fsl: assign job-rings to non-TrustZone"Breno Matheus Lima2019-06-112-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 22191ac35344 ("drivers/crypto/fsl: assign job-rings to non-TrustZone") breaks HABv4 encrypted boot support in the following i.MX devices: - i.MX6UL - i.MX7S - i.MX7D - i.MX7ULP For preparing a HABv4 encrypted boot image it's necessary to encapsulate the generated DEK in a blob. In devices listed above the blob generation function takes into consideration the Job Ring TrustZone ownership configuration (JROWN_NS) and can be only decapsulated by the same configuration. The ROM code expects DEK blobs encapsulated by the Secure World environments which commonly have JROWN_NS = 0. As U-Boot is running in Secure World we must have JROWN_NS = 0 so the blobs generated by dek_blob tool can be decapsulated by the ROM code. Job-rings assignment is now handled in OP-TEE OS, this commit can be safely reverted. https://github.com/OP-TEE/optee_os/pull/2986 This reverts commit 22191ac353445ad8fafc5a78aefcd94e78963041. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Acked-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
* regulator: bd71837: copy the bd71837 pmic driver from NXP imx u-bootMatti Vaittinen2019-06-113-0/+97
| | | | | | | | | | | | https://source.codeaurora.org/external/imx/uboot-imx cherry picked, styled and merged commits: - MLK-18387 pmic: Add pmic driver for BD71837: e9a3bec2e95a - MLK-18590 pmic: bd71837: Change to use new fdt API: acdc5c297a96 Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* power: pfuze100: Fix off by one error in voltage table handlingTrent Piepho2019-06-111-2/+2
| | | | | | | | | | | The code that sets a regulator by looking up the voltage in a table had an off by one error. vsel_mask is a bitmask, not the number of table entries, so a vsel_mask value of 0x7 indicates there are 8, not 7, entries in the table. Cc: Peng Fan <Peng.Fan@freescale.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com>
* Merge tag 'efi-2019-07-rc4' of git://git.denx.de/u-boot-efiTom Rini2019-06-021-1/+1
|\ | | | | | | | | | | | | | | | | | | Pull request for UEFI sub-system for v2019.07-rc4 Corrections for boottime services for protocols and for the SetTime() service are provided. Error messages for the 'setenv -e' and 'bootefi bootmgr' commands are added.
| * rtc: export rtc_month_days()Heinrich Schuchardt2019-05-311-1/+1
| | | | | | | | | | | | Export function rtc_month_days() for reuse in the UEFI subsystem. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | dm: net: macb: Implement link speed change callbackBin Meng2019-06-011-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the link speed change callback is a nop. According to macb device tree bindings, an optional "tx_clk" is used to clock the ethernet controller's TX_CLK under different link speed. In 10/100 MII mode, transmit logic must be clocked from a free running clock generated by the external PHY. In gigabit GMII mode, the controller, not the external PHY, must generate the 125 MHz transmit clock towards the PHY. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | dm: net: macb: Update macb_linkspd_cb() signatureBin Meng2019-06-011-1/+21
| | | | | | | | | | | | | | | | | | This updates DM version macb_linkspd_cb() signature for future expansion, eg: adding an implementation for link speed changes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | clk: sifive: Add clock driver for GEMGXL MGMTBin Meng2019-06-013-0/+69
|/ | | | | | | | | | This adds a clock driver to support the GEMGXL management IP block found in FU540 SoCs to control GEM TX clock operation mode for 10/100/1000 Mbps. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* Merge tag 'rockchip-for-v2019.07-rc3' of git://git.denx.de/u-boot-rockchipTom Rini2019-05-311-0/+2
|\ | | | | | | | | | | | | - some fix for rk3399-puma; - rockchip script make_fit_atf.py cleanup - Enable TPL for rk3399 orangepi and nanopi4; - add support for rk3399 boards: Nanopi NEO4, Rockpro64, Rock PI 4;
| * rockchip: clk: rk3399: allow requests for all UART clocksChristoph Muellner2019-05-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the rate for UART1 and UART3 the same way as already implemented for UART0 and UART2. This is required for boards, which have their console output on these UARTs. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | clk: meson-g12a: Add PCIE PLL supportNeil Armstrong2019-05-311-0/+103
|/ | | | | | | The G12A PCIE PLL clock was introduced in Linux 5.2-rc1, and is needed for USB to operate, add basic support for it and associated gates. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2019-05-296-0/+518
|\ | | | | | | - Audio support
| * sound: tegra: Add a sound driverSimon Glass2019-05-242-1/+101
| | | | | | | | | | | | | | | | Add a sound driver for tegra devices. This connects the audio hub, I2S controller and audio codec to allow sound output. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: sound: Add an I2S driverSimon Glass2019-05-243-1/+153
| | | | | | | | | | | | | | | | | | | | Add a driver which supports transmitting digital sound to an audio codec. This uses fixed parameters as a device-tree binding is not currently defined. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: sound: Add an audio hub driverSimon Glass2019-05-243-0/+266
| | | | | | | | | | | | | | | | | | Add a driver for the audio hub. This is modelled as a misc device which supports writing audio data from I2S. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | dm: arm: bcmstb: Enable driver model MMC supportThomas Fitzsimmons2019-05-281-18/+55
| | | | | | | | | | | | | | | | | | | | For bcm7445 and bcm7260, this patch enables CONFIG_DM_MMC and updates the bcmstb SDHCI driver to use the new driver model. This allows removal of SDHCI configuration handling from bcmstb.c, and eliminates a board removal compile warning. Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org> Reviewed-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2019-05-265-13/+596
|\ \ | | | | | | | | | | | | | | | - Gen3 PCIe driver + enablement on Salvator-X platforms. - Gen3 recovery SPL used to reload ATF/OpTee/U-Boot instead of minimon. - SDHI HS400 fixes ported from latest BSP and datasheet.
| * | mmc: tmio: sdhi: HS400 manual adjustmentMarek Vasut2019-05-212-3/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since Gen3 SDHI has an internal DS signal AC-spec violation in HS400 mode, CRC-error may occur in read command in HS400 mode. This phoenomenon occurs at low/high temperature. To fix this, after completion of HS400 tuning, enable manual calibration. However, Gen3 M3 Ver.1.2 or earlier and H3 1.x does not support HS400. These SoC forcibly use HS200 mode by SoC attribute. The DT adjustment of the tuning parameters is not supported until the DT property names become clear. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Adapted from a patch by Takeshi Saito <takeshi.saito.xv@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Peng Fan <peng.fan@nxp.com>
| * | mmc: tmio: sdhi: Minor macro cleanupMarek Vasut2019-05-211-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | Clean up the whitespaces in macros, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Peng Fan <peng.fan@nxp.com>
| * | pci: renesas: Add RCar Gen3 PCIe controller driverMarek Vasut2019-05-213-0/+420
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for the Renesas RCar PCIe controller present on Gen3 SoCs. The PCIe on Gen3 is used both to connect external PCIe peripherals. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2019-05-261-3/+2
|\ \ \ | | | | | | | | | | | | - SoCFPGA PL310 cleanup + A10 fix, A10 DT cleanup, DW GPIO fix.
| * | | gpio: dwapb_gpio: fix broken dev->nodeSimon Goldschmidt2019-05-241-3/+2
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 1b898ffc040b ("gpio: dwapb_gpio: convert to livetree") introduced a bug in that dev->node of the gpio chip was accidentally set to the of_node of its bank subnode. What it meant to do was assign subdev->node, not dev->node. While this doesn't affect too many use cases, iterating over the gpio chip's properties doesn't work any more after that, so fix this. Fixes: commit 1b898ffc040b ("gpio: dwapb_gpio: convert to livetree") Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* | | configs: Migrate CONFIG_FMAN_ENET and some related options to KconfigTom Rini2019-05-263-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the main symbol for Freescale Fman Ethernet controller option to Kconfig. Also migrate the CONFIG_SYS_QE_FMAN_FW_IN_xxx macros and rename the SPIFLASH one to follow the same format as all of the others. To do this fully we need to migrate CONFIG_QC, do so. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | Merge tag 'u-boot-stm32-20190523' of https://github.com/pchotard/u-bootTom Rini2019-05-2413-39/+3814
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add various STM32MP1 fixes for serial, env, clk, board, i2c ... - Add STM32MP1 DDR driver update: These update introduce the DDR interactive mode described in: https://wiki.st.com/stm32mpu/index.php/U-Boot_SPL:_DDR_interactive_mode This mode is used by the CubeMX: DDR tuning tool. https://wiki.st.com/stm32mpu/index.php/STM32CubeMX The DDR interactive mode is NOT activated by default because it increase the SPL size and slow down the boot time (200ms wait added).
| * | | stm32mp1: ram: add tuning in DDR interactive modePatrick Delaunay2019-05-236-1/+1414
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add command tuning for DDR interactive mode, used during board bring-up or with CubeMX DDR tools to execute software tuning for the DDR configuration: - software read DQS Gating (replace the built-in one) - Bit de-skew - Eye Training or DQS training Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: ram: add tests in DDR interactive modePatrick Delaunay2019-05-235-0/+1541
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add command tests for DDR interactive mode, used during board bring-up or with CubeMX DDR tools to verify the DDR configuration. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: ram: add interactive mode for DDR configurationPatrick Delaunay2019-05-234-0/+713
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This debug mode is used by CubeMX DDR tuning tools or manualy for tests during board bring-up. It is simple console used to change DDR parameters and check initialization. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: ram: add support for LPDDR2/LPDDR3Patrick Delaunay2019-05-232-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Manage power supply configuration for board using stpmic1 with LPDDR2 or with LPDDR3: + VDD_DDR1 = 1.8V with BUCK3 (bypass if possible) + VDD_DDR2 = 1.2V with BUCK2 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: ram: update parameter array initializationPatrick Delaunay2019-05-232-16/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Force alignment of the size of parameters array with the expected value in the binding, that allows compilation error when the array size change. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: ram: change ddr speed to kHzPatrick Delaunay2019-05-233-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | Allow fractional support in DDR tools. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: ram: increase the delay after reset to 128 cyclesPatrick Delaunay2019-05-231-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Component Notification DDR controller errata (3.00a):9001313030 Synchronization Time Waited After De-assertion of presetn is 128 pclk Cycles. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: ram: update mask for operating modePatrick Delaunay2019-05-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Regression introduced by rebase, when loop was replaced by readl_poll_timeout() function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | serial: stm32: remove watchog reset in debug putcPatrick Delaunay2019-05-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For STM32MP, the watchdog is based on DM and the function watchod_reset call the function uclass_get_device(UCLASS_WDT) to found the driver associated IWDG2. As this reset is not mandatory in debug putc (the uart fifo will be empty after some us), we can simplify the code by removing this call. And this patch avoid issue when putc is called before initialization of DM core, before the parsing of the device tree parsing and each node bound to driver; that also avoid memory leak. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | serial: stm32: remove unnecessary tracePatrick Delaunay2019-05-231-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove the trace indicating the end of the DEBUG initialization Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | clk: stm32mp1: add set_rate for DDRPHYC clockPatrick Delaunay2019-05-231-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | Add the DDRPHYC support for clk_set_rate, used in DDR interactive mode Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | i2c: stm32f7: improve loopback in timing algorithmNicolas Le Bayon2019-05-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This avoids useless loops inside the I2C timing algorithm. Actually, we support only one possible solution per prescaler value. So after finding a solution with a prescaler, the algorithm can switch directly to the next prescaler value. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | i2c: stm32f7: Fix SDADEL minimum formulaNicolas Le Bayon2019-05-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It conforms with Reference Manual I2C timing section. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | | | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2019-05-246-2/+1061
|\ \ \ \ | | | | | | | | | | | | | | | - Enable DM for SATA, SDHC, USB in T2080QDS
| * | | | ata: fsl_ahci: Add sata DM support for Freescale powerpc socsPeng Ma2019-05-234-0/+1042
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to support Freescale sata driver with dts initialized. Also resolved the following problems. ===================== WARNING ====================== This board does not use CONFIG_DM_SCSI. Please update the storage controller to use CONFIG_DM_SCSI before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ==================================================== Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | | usb: ehci: adopt 32 bit address for CONFIG_PPCYinbo Zhu2019-05-231-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | adopt 32 bit addr in fsl_esdhc for CONFIG_PPC. So adopt 32 bit address for CONFIG_PPC. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | | driver: mmc: adopt 32 bit addr in fsl_esdhc for CONFIG_PPCYinbo Zhu2019-05-231-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PowerPC supports 32 bit address. So adopt 32 bit addr in fsl_esdhc for CONFIG_PPC. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | | driver: mmc: set sdhc clock in fsl_esdhc for CONFIG_PPCYinbo Zhu2019-05-231-0/+6
| |/ / / | | | | | | | | | | | | | | | | Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | | | drivers: serial: mcfuart: add DT supportAngelo Dureghello2019-05-242-78/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds devicetree support to the mcfuart.c driver and removes non DM code. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* | | | drivers: spi: cf_spi: convert to driver modelAngelo Dureghello2019-05-241-177/+305
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Converting to driver model and removes non-dm code. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* | | | drivers: spi: cf_spi: add Kconfig optionAngelo Dureghello2019-05-241-0/+6
| |/ / |/| | | | | | | | | | | | | | | | | This patch adds cf_spi DM Kconfig option. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* | | Merge tag 'dm-pull-22may19' of git://git.denx.de/u-boot-dmTom Rini2019-05-224-8/+89
|\ \ \ | |/ / |/| | | | | | | | Various DM fixes Addition of ofnode_get_addr_size_index()
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