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* Merge git://git.denx.de/u-boot-x86Tom Rini2018-10-222-3/+16
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| * x86: tsc: Introduce config option for early timer frequencyBin Meng2018-10-222-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far the TSC timer driver supports trying hardware calibration first and using device tree as last resort for its running frequency as the normal timer. However when it is used as the early timer, it only supports hardware calibration and if it fails, the driver just panics. This introduces a new config option to specify the early timer frequency in MHz and it should be equal to the value described in the device tree. Without this patch, the travis-ci testing on QEMU x86_64 target fails each time after it finishes the 'bootefi selftest' as the test.py see an error was emitted on the console like this: TSC frequency is ZERO resetting ... ### ERROR ### Please RESET the board ### It's strange that this error is consistently seen on the travis-ci machine, but only occasionally seen on my local machine (maybe 1 out of 10). Since QEMU x86_64 target enables BOOTSTAGE support which uses early timer, with this fix it should work without any failure. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * Enable CONFIG_TIMER_EARLY with bootstageSimon Glass2018-10-221-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In initr_bootstage() we call bootstage_mark_name() which ends up calling timer_get_us(). This call happens before initr_dm(), which inits driver model. On x86 we set gd->timer to NULL in the transition from board_init_f() to board_init_r(). See board_init_f_r() for this assignment. So U-Boot knows there is no timer available in the period immediately after relocation. On x86 the timer_get_us() call is implemented as calls to get_ticks() and get_tbclk(). Both of these call dm_timer_init() to set up the timer, if gd->timer is NULL and the early timer is not available. However dm_timer_init() cannot succeed before initr_dm() is called. So it seems that on x86 if we want to use CONFIG_BOOTSTAGE we must enable CONFIG_TIMER_EARLY. Update the Kconfig to handle this. Note: On most architectures we can rely on the pre-relocation memory still being available, so that gd->timer pointers to a valid timer device and everything works correctly. Admittedly this is not strictly correct since the timer device is set up by pre-relocation U-Boot, but normally this is fine. On x86 the 'CAR' (cache-as-RAM) memory used by pre-relocation U-Boot disappears in board_init_f_r() and any attempt to access it will hang. This is the reason why we must mark the timer as invalid when we get to board_init_f_r(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | watchdog: aspeed: restore default value of reset_maskCédric Le Goater2018-10-221-0/+1
| | | | | | | | | | | | | | | | This is required for the current Linux kernel to reboot. It should also probably be fixed in Linux. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | nand: atmel: Initialize pmecc smu with correct sizeBin Meng2018-10-221-1/+1
|/ | | | | | | | | | | | | | | | | | Currently in pmecc_get_sigma(), the code tries to clear the memory pointed by smu with wrong size 'sizeof(int16_t) * ARRAY_SIZE(smu)'. Since smu is actually a pointer, not an array, so ARRAY_SIZE(smu) does not generate correct size to be cleared. In fact, GCC 8.1.0 reports a warning against it: error: division 'sizeof (int16_t * {aka short int *}) / sizeof (int16_t {aka short int})' does not compute the number of array elements [-Werror=sizeof-pointer-div] Fix it by using the correct size. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
* pci: Support parsing PCI controller DT subnodesMarek Vasut2018-10-201-3/+29
| | | | | | | | | | | | | The PCI controller can have DT subnodes describing extra properties of particular PCI devices, ie. a PHY attached to an EHCI controller on a PCI bus. This patch parses those DT subnodes and assigns a node to the PCI device instance, so that the driver can extract details from that node and ie. configure the PHY using the PHY subsystem. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Convert CONFIG_FLASH_CFI_DRIVER et al to KconfigAdam Ford2018-10-191-0/+38
| | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_FLASH_CFI_DRIVER CONFIG_SYS_FLASH_USE_BUFFER_WRITE CONFIG_FLASH_CFI_MTD CONFIG_SYS_FLASH_PROTECTION CONFIG_SYS_FLASH_CFI Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Re-migrate] Signed-off-by: Tom Rini <trini@konsulko.com>
* bootcount: Make bootcount magic configurableMarek Vasut2018-10-195-12/+19
| | | | | | | | | Add new Kconfig option, SYS_BOOTCOUNT_MAGIC, to select the boot counter magic word. This can be useful ie. in case the entire boot counter register is not usable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-microblazeTom Rini2018-10-164-4/+8
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx changes for v2018.11-rc2-v2 FPGA: - Fix SPL fpga loading from FIT ARM64: - Fix gic accesses in EL2/EL1 Xilinx: - Add dlc20 board support - Add Versal board support - Sync defconfigs - Enable MP via Kconfig - Add missing efuse node - Enable CDC for zcu100 cmd: - Fix kgdb Kconfig dependency
| * net: gem: Do not setup any clock for Xilinx SoC VersalMichal Simek2018-10-161-0/+4
| | | | | | | | | | | | | | Xilinx SoC Versal is using fixed clock where setting rate is not supported. That's why workaround the driver till real clock driver is supported. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: versal: Add support for new Xilinx Versal ACAPsMichal Simek2018-10-163-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2018-10-162-0/+8
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| * i2c: fix: Add support for the Arm's Versatile Express I2C controllerHeiko Schocher2018-10-122-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | accidentially while fixing merge errors for patch: https://lists.denx.de/pipermail/u-boot/2018-September/342278.html missed to add files: MAINTAINERS drivers/i2c/Kconfig drivers/i2c/Makefile add them with this patch. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Liviu Dudau <liviu.dudau@foss.arm.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2018-10-124-20/+39
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| * | sf: Add MICRON manufacturer idAshish Kumar2018-10-122-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NOR flash name MT35X_QLKA and MT25Q_** used on NXP board has manufacturer id as 0x2C, which are rather for newer flashes after the split of Micron from ST. So macro for this micron manufacturer id. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> [jagan: updated commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | spi: davinci: Add platdata supportJagan Teki2018-10-101-19/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | Davanci spi driver has DM support already, this patch add support for platdata so-that SPL can use it for low foot-print. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Adam Ford <aford173@gmail.com>
| * | mtd: uboot: Fix hanging during mtd list commandAdam Ford2018-10-101-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards (like omap3_logic) hang when trying to access address 0. This happens when executing the new 'mtd list' command. This patch enhances the checks for conditions that would preclude mtd_probe_devices() from operating. Fixes: 5db66b3aee6f ("cmd: mtd: add 'mtd' command") Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
* | | ldpaa_eth.c: Fix warning when PHYLIB is not enabledTom Rini2018-10-121-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | We need to #ifdef some variables to avoid warning about them being unused. Fixes: 1a048cd65645 ("driver: net: fsl-mc: Add support of multiple phys for dpmac") Signed-off-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2018-10-1118-245/+567
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| * | driver: net: fsl-mc: Add support of multiple phys for dpmacPankaj Bansal2018-10-102-43/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Till now we have had cases where we had one phy device per dpmac. Now, with the upcoming products (LX2160AQDS), we have cases, where there are sometimes two phy devices for one dpmac. One phy for TX lanes and one phy for RX lanes. to handle such cases, add the support for multiple phys in ethernet driver. The ethernet link is up if all the phy devices connected to one dpmac report link up. also the link capabilities are limited by the weakest phy device. i.e. say if there are two phys for one dpmac. one operates at 10G without autoneg and other operate at 1G with autoneg. Then the ethernet interface will operate at 1G without autoneg. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | driver: net: fsl-mc: initialize dpmac irrespective of phyPankaj Bansal2018-10-101-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The dpmac initalization should not depend on phy. As the phy is not necessary to be present for dpmac to function. Therefore, remove dpmac initialization dependency from phy. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | driver: net: fsl-mc: Modify the dpmac link detection methodPankaj Bansal2018-10-101-62/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when there is no phy present for a dpmac, a dummy phy device is created. when we move to multiple phy method, we need to create as many dummy phy devices. Change this method so that we don't need to create dummy phy devices. We always report linkup if no phy is present. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | driver: net: fsl-mc: fix error handing in init_phyPankaj Bansal2018-10-101-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | if an error occurs during init_phy, we should free the phydev structure which has been allocated by phy_connect. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | driver: net: fsl-mc: remove unused strcture elementsPankaj Bansal2018-10-103-27/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The phydev structure is present in both ldpaa_eth_priv and wriop_dpmac_info. the phydev in wriop_dpmac_info is not being used As the phydev is created based on phy_addr and bus members of wriop_dpmac_info, it is appropriate to keep phydev in wriop_dpmac_info. Also phy_regs is not being used, therefore remove it Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | driver: net: fsl-mc: modify the label namePankaj Bansal2018-10-101-4/+4
| | | | | | | | | | | | | | | | | | | | | The goto label name is misspelled it should be DPMAC not DPAMC Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | test: eth: Add a test for the target being pingedJoe Hershberger2018-10-101-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The target will respond to pings while doing other network handling. Make sure that the response happens and is correct. This currently corrupts the ongoing operation of the device if it happens to be awaiting an ARP reply of its own to whatever serverip it is attempting to communicate with. In the test, add an expectation that the user operation (ping, in this case) will fail. A later patch will address this problem. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | test: eth: Add a test for ARP requestsJoe Hershberger2018-10-101-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This tests that ARP requests made to this target's IP address are responded-to by the target when it is doing other networking operations. This currently corrupts the ongoing operation of the device if it happens to be awaiting an ARP reply of its own to whatever serverip it is attempting to communicate with. In the test, add an expectation that the user operation (ping, in this case) will fail. A later patch will address this problem. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | net: sandbox: Add a priv ptr for tests to useJoe Hershberger2018-10-101-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | Tests need to be able to pass their "unit test state" to the handlers where asserts are evaluated. Add a function that allows the tests to set this private data on the sandbox eth device. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | net: sandbox: Allow fake eth to handle more than 1 packet responseJoe Hershberger2018-10-101-11/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use up to the max allocated receive buffers so as to be able to test more complex situations. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | net: sandbox: Share the priv structure with testsJoe Hershberger2018-10-101-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | If tests want to implement tx handlers, they will likely need access to the details in the priv structure. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | net: sandbox: Make the fake eth driver response configurableJoe Hershberger2018-10-101-4/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make the send handler registerable so tests can check for different things. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | net: sandbox: Refactor sandbox send functionJoe Hershberger2018-10-101-74/+106
| | | | | | | | | | | | | | | | | | | | | Make the behavior of the send function reusable. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | net: sandbox: Move disabled flag into priv structJoe Hershberger2018-10-101-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | Store the per-device data with the device. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | net: phy: ti: Add binding for the CLK_OUT pin muxingJanine Hagemann2018-10-101-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DP83867 has a muxing option for the CLK_OUT pin. It is possible to set CLK_OUT for different channels. Create a binding to select a specific clock for CLK_OUT pin. Based on commit 9708fb630d19 ("net: phy: dp83867: Add binding for the CLK_OUT pin muxing option") of mainline linux kernel. Signed-off-by: Janine Hagemann <j.hagemann@phytec.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: ti: Recover from "port mirroring" N/A MODE4Janine Hagemann2018-10-101-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DP83867 when not properly bootstrapped - especially with LED_0 pin - can enter N/A MODE4 for "port mirroring" feature. To provide normal operation of the PHY, one needs not only to explicitly disable the port mirroring feature, but as well stop some IC internal testing (which disables RGMII communication). To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit 11 examined. When it is set, the another RESERVED bit (11) at PHYCR (0x0010) register must be clear to disable testing mode and enable RGMII communication. Thorough explanation of the problem can be found at following e2e thread: "DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) - Linux driver" https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954 Based on commit ac6e058b75be ("net: phy: dp83867: Recover from "port mirroring" N/A MODE4") of mainline linux kernel. Signed-off-by: Janine Hagemann <j.hagemann@phytec.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Lukasz Majewski <lukma@denx.de>
| * | net: phy: ti: Add lane swapping support in the DP83867 TI's PHY driverJanine Hagemann2018-10-101-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for enabling or disabling the lane swapping (called "port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY device. One use case is when bootstrap configuration enables this feature (because of e.g. LED_0 wrong wiring) so then one needs to disable it in software (at u-boot/Linux). Based on commit fc6d39c39581 ("net: phy: dp83867: Add lane swapping support in the DP83867 TI's PHY driver") of mainline linux kernel. Signed-off-by: Janine Hagemann <j.hagemann@phytec.de> Acked-by: Lukasz Majewski <lukma@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net.h: Include linux/if_ether.h to avoid duplicationBin Meng2018-10-1010-30/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are plenty of existing drivers that have macros like ETH_ALEN defined in their own source files. Now that we imported the kernel's if_ether.h to U-Boot we can reduce some duplication. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: pch_gbe: Make probe/remove staticBin Meng2018-10-091-2/+2
| | | | | | | | | | | | | | | | | | | | | These two routines are internal to pch_gbe driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | linux/compat.h: Add netdev_### log macrosBin Meng2018-10-092-18/+0
| |/ | | | | | | | | | | | | | | | | Currently there are two ethernet drivers (mvneta.c and mvpp2.c) that has netdev_### (eg: netdev_dbg) log macros defined in its own driver file. This adds these log macros in a common place linux/compat.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge tag 'dm-9oct18' of git://git.denx.de/u-boot-dmTom Rini2018-10-1038-397/+792
|\ \ | | | | | | | | | | | | | | | Test improvements to tidy up output and drop duplicate tests Sandbox SPL/TPL support Various dm-related improvements
| * | video: at91: Adjust vidconsole_position_cursor() to use char posSimon Glass2018-10-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present this function uses pixels but it seems more useful for it to position in terms of characters on the screen. This also matches the comment to the function. Update this. Unfortunately there is one user of this function (at91). Have a crack at fixing this, since I cannot test it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
| * | sysreset: Add a way to find the last resetSimon Glass2018-10-092-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | We have a method to return the last reset as a string for humans, but not a method that allows it to be used programmatically. Add a new method that returns the last reset as an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | sysreset: Tidy up a few comments and loggingSimon Glass2018-10-091-1/+3
| | | | | | | | | | | | | | | | | | | | | Some comments are incorrect or missing pieces. Fix these and use logging to print the error. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | pci: Add a little more debugging to pci_romSimon Glass2018-10-091-2/+2
| | | | | | | | | | | | | | | | | | | | | Add some logging on failure. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | ctags: Minor changes to fix ctags outputSimon Glass2018-10-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present ctags emits lines with unmatched quotes which means that the output file is invalid. This is with exuberant-ctags version 5.9~svn201103 but I also see it with plain ctags. I am not sure that it is a bug though. Make a few minor changes in the source code to fix this problem. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | panel: Expand the backlight supportSimon Glass2018-10-094-36/+199
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the panel can be turned on but not off, and the brightness cannot be controlled at run-time. Add a new API function to both the panel and backlight uclasses to handle this. Enhance the PWM backlight driver to deal with custom levels properly and allow the backlight to be turned on and off. Update the test to cover thes new features. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | test: panel: Add a test for the panel uclassSimon Glass2018-10-091-0/+25
| | | | | | | | | | | | | | | | | | | | | At present this uclass has no tests. Add a simple one which checks the PWM configuration, regulator and GPIO. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | cros_ec: Add support for v3 messages on LPCSimon Glass2018-10-091-0/+33
| | | | | | | | | | | | | | | | | | | | | At present version 3 messages are only supported on SPI. Add support for using LPC as well, as used on samus. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | cros_ec: Update cros_ec_read_hash() to specify the imageSimon Glass2018-10-091-3/+4
| | | | | | | | | | | | | | | | | | Allow selection of which EC image to hash. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | cros: Update ec_commands to latest versionSimon Glass2018-10-092-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This file has changed quite a bit in the last 5 years as the capabilities of the ECs have grown. Sync it up with the copy in coreboot commit b9141f2215. The only change is the addition of EC_VBNV_BLOCK_SIZE_V2. This is needed because U-Boot uses the new v2 vboot API and this is not currently fully supported by Chromium OS firmware. Signed-off-by: Simon Glass <sjg@chromium.org>
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