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* Merge tag 'xilinx-for-v2017.09' of git://www.denx.de/git/u-boot-microblazeTom Rini2017-08-042-162/+556
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx changes for v2017.09 Zynq: - Add Z-Turn board support fpga: - Remove intermediate buffer from code Zynqmp: - dts cleanup - change psu_init handling - Add options to get silicon version - Fix time handling - Map OCM/TCM via MMU - Add new clock driver
| * fpga: xilinx: Avoid using local intermediate bufferSiva Durga Prasad Paladugu2017-08-021-16/+10
| | | | | | | | | | | | | | | | | | Dont use local temporary buffer for printing out the info instead use directly from memroy. This fixes the issue of stack corruprion due to local buffer overflow. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * clk: zynqmp: Remove unused macros/variablesMichal Simek2017-08-021-4/+0
| | | | | | | | | | | | | | | | These macros and one variable is not used anywhere that's why they should be removed. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * clk: zynqmp: Dont panic incase of mmio write/read failuresSiva Durga Prasad Paladugu2017-08-021-19/+44
| | | | | | | | | | | | | | | | | | | | Dont panic incase of mmio write/read failures instead return error and let the peripheral driver take care of clock get and set failures. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * clk: zynqmp: Add support for CCF driverSiva Durga Prasad Paladugu2017-08-021-147/+526
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for CCF, this CCF reads the ref clocks from dt and checks all the required clock control registers for its source , divisors and calculates the clock from them. This supports clock and set functions. Panic when read/write fails. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ahci-pci: Update call to ahci_probe_scsi_pci()Bin Meng2017-08-031-1/+1
| | | | | | | | | | | | | | | | | | ahci_probe_scsi() now takes a 'base' argument, and there is an API that prepares base address for us: ahci_probe_scsi_pci(). Reported-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2017-08-028-7/+1046
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| * | net: ravb: Add clock handling supportMarek Vasut2017-08-031-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for enabling and disabling the clock using the clock framework based on the content of OF instead of doing it manually in the board file. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | net: ravb: Detect PHY correctlyMarek Vasut2017-08-031-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The order of parameters passed to the phy_connect() was wrong. Moreover, only PHY address 0 was used. Replace this with code capable of detecting the PHY address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | net: ravb: Add OF probing supportMarek Vasut2017-08-031-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for probing the RAVB Ethernet block from device tree. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | serial: sh: Use the clock framework to obtain clock configMarek Vasut2017-08-031-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we now have clock driver on the RCar Gen3 , obtain the clock configuration using the clock framework functions. In case this fails, fall back to the original code for pulling the clock config directly out of OF. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | serial: sh: Convert to KconfigMarek Vasut2017-08-031-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the SH Serial to Kconfig using tools/moveconfig.py tool and a bit of manual adjustment to cater for failed conversions. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | clk: rmobile: Add RCar Gen3 clock driverMarek Vasut2017-08-035-0/+967
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock driver for the RCar Gen3 R8A7795 and R8A7796 SoCs . This driver allows reading out the clock configuration set by previous boot stages and enabling and disabling clock using the MSTP registers. Setting clock is not supported thus far. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-08-023-2/+14
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/ls1046aqds.h include/configs/ls1046ardb.h
| * | soc/fsl-layerscape: Update SVR number for LS2081A and LS2041ASantan Kumar2017-08-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update SVR as per the SOC document. -LS2081A: 0x870919 -> 0x870918 -LS2041A: 0x870915 -> 0x870914 Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | fsl/usb: enable errata-a010151 for ls2088a and ls2081aSantan Kumar2017-08-011-0/+4
| | | | | | | | | | | | | | | Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | spi: fsl_qspi: Pet watchdog even moreAlexander Stein2017-08-011-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pet the watchdog once upon each command call (qspi_xfer) and during each loop iteration in several commands. This fixes a watchdog reset especially during erase command. Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge git://git.denx.de/u-boot-x86Tom Rini2017-08-019-57/+141
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| * | | x86: Convert MMC to driver modelSimon Glass2017-08-011-26/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the pci_mmc driver over to driver model and migrate all x86 boards that use it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: remove DM_MMC from edison_defconfig] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | | block: ide: Fix build error when CONFIG_BLK is onBin Meng2017-08-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing #ifndef CONFIG_BLK to wrap dev_desc->block_read. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | dm: scsi: Add a generic PCI-based AHCI driverBin Meng2017-08-013-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for PCI-based AHCI controller based on DM SCSI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * | | x86: Convert INTEL_ICH6_GPIO to KconfigBin Meng2017-08-011-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts Intel ICH6 GPIO driver to Kconfig, and add it to the imply list of platform drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | x86: kconfig: Select PCI and DM_PCIBin Meng2017-08-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI is the de facto interconnect bus in an x86 system. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | x86: kconfig: Select TIMER and X86_TSC_TIMERBin Meng2017-08-011-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without a timer, U-Boot just doesn't boot. This is not something we can turn off. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | x86: tsc: Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr()Bin Meng2017-08-011-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr(), as that better describes what the routine does. This keeps in sync with Linux kernel commit: 02c0cd2: x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | x86: tsc: Correct Silvermont reference clock valuesBin Meng2017-08-011-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Atom processors use a 19.2 MHz crystal oscillator. Early processors generate 100 MHz via 19.2 MHz * 26 / 5 = 99.84 MHz. Later processors generate 100 MHz via 19.2 MHz * 125 / 24 = 100 MHz. Update the Silvermont-based tables accordingly, matching the Software Developers Manual. Also, correct a 166 MHz entry that should have been 116 MHz, and add a missing 80 MHz entry for VLV2. This keeps in sync with Linux kernel commit: 05680e7: x86/tsc_msr: Correct Silvermont reference clock values Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | x86: tsc: Update comments and expand definitions in freq_desc_tables[]Bin Meng2017-08-011-15/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some processor abbreviations in the comments of freq_desc_tables[] are obscure. This updates part of these to mention processors that are known to us. Also expand frequency definitions. This keeps in sync with Linux kernel commit: 9e0cae9: x86/tsc_msr: Update comments, expand definitions Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | x86: tsc: Remove the fail handling in try_msr_calibrate_tsc()Bin Meng2017-08-011-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If either ratio or freq is zero, the return value is zero. There is no need to create a fail branch and return zero there. This keeps in sync with Linux kernel commit: 14bb4e3: x86/tsc_msr: Remove debugging messages Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | x86: tsc: Identify Intel-specific codeBin Meng2017-08-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | try_msr_calibrate_tsc() is currently Intel-specific, and should not execute on any other vendor's parts. This keeps in sync with Linux kernel commit: ba82683: x86/tsc_msr: Identify Intel-specific code Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | x86: tsc: Read all ratio bits from MSR_PLATFORM_INFOBin Meng2017-08-011-1/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we read the tsc radio like this: ratio = (MSR_PLATFORM_INFO >> 8) & 0x1f; Thus we get bit 8-12 of MSR_PLATFORM_INFO, however according to the Intel manual, the ratio bits are bit 8-15. Fix this problem by masking 0xff instead. This keeps in sync with Linux kernel commit: 886123f: x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | regulator: palmas: disable bypass when the LDO is enabledJean-Jacques Hiblot2017-08-011-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some LDOs have a bypass capability. Make sure that the bypass is disabled when is the LDO is enabled (otherwise the voltage can't be changed). Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | regulator: palmas: Add support for LDO1 regulator to provide 1.8VKishon Vijay Abraham I2017-08-011-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify palmas_mmc1_poweron_ldo() API to set the voltage based on the voltage parameter passed as argument instead of always setting it to 3.0V. This allows MMC1 to set the LDO1 regulator voltage to 3.3V or 1.8V. 1.8V is required to add support for UHS mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | dm: mmc: sunxi: Add support for driver modelSimon Glass2017-08-011-0/+133
| | | | | | | | | | | | | | | | | | | | | Add a driver-model version of this driver which mostly uses the existing code. The old code can be removed once all boards are switched over. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: mmc: sunxi: Drop mmc_clk_io_on()Simon Glass2017-08-011-24/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function has #ifdefs in it which we want to avoid for driver model. Instead we should use different compatible strings and the .data field. It also uses the MMC device number which is not available in driver model except through aliases. Move the function's into its caller so that the driver-model version can do things its own way. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | | dm: mmc: sunxi: Pass private data around explicitlySimon Glass2017-08-011-29/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the driver-private data is obtained in various functions by various means. With driver model this is provided automatically. Without driver model it comes from a C array declared at the top of the file. Adjust internal functions so that they are passed the private data as a parameter, allowing the caller to obtain it using either means. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | | dm: mmc: sunxi: Rename mmchost to privSimon Glass2017-08-011-63/+62
| | | | | | | | | | | | | | | | | | | | | | | | Use the driver-model naming convention for this structure. It is data private to the driver so the local variable should be called 'priv'. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | | dm: mmc: sunxi: Rename struct sunxi_mmc_host to sunxi_mmc_privSimon Glass2017-08-011-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | Use the driver-model naming convention for this structure. It is data private to the driver. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | | dm: ahci: Correct uclass private dataSimon Glass2017-08-012-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is expected to be attached to the uclass and the code operates that way, but the uclass has not been updated. Fix it to avoid using memory at address 0. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 47fc61a (dm: ahci: Drop use of probe_ent)
* | | dm: scsi: Drop duplicate SCSI and DM_SCSI optionsSimon Glass2017-08-011-18/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | When the SATA code was moved into drivers/ata these Kconfig options were added to that directory. They already exist in drivers/scsi. Remove them from drivers/ata to fix the duplication. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 7f2b5f4 (sata: Move drivers into new drivers/ata directory)
* | | dm: mmc: Allow disabling driver model in SPLSimon Glass2017-08-0110-36/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present if U-Boot proper uses driver model for MMC, then SPL has to also. While this is desirable, it places a significant barrier to moving to driver model in some cases. For example, with a space-constrained SPL it may be necessary to enable CONFIG_SPL_OF_PLATDATA which involves adjusting some drivers. Add new SPL versions of the options for DM_MMC, DM_MMC_OPS and BLK. By default these follow their non-SPL versions, but this can be changed by boards which need it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | ahci: Support non-PCI controllersSimon Glass2017-08-011-9/+17
|/ / | | | | | | | | | | | | | | At present the AHCI SCSI driver only supports PCI with driver model. Rename the existing function to indicate this and add support for adding a non-PCI controller . Signed-off-by: Simon Glass <sjg@chromium.org>
* | configs: Migrate CMD_NAND*Tom Rini2017-07-311-0/+7
| | | | | | | | | | | | | | | | | | | | Migrate all remaining instances of CMD_NAND, CMD_NAND_TRIMFFS CMD_NAND_LOCK_UNLOCK and CMD_NAND_TORTURE from the headers into the defconfig files. Tested-by: Adam Ford <aford173@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: console: Check for serial devices properlySimon Glass2017-07-311-1/+1
| | | | | | | | | | | | | | | | | | With driver model the serial device is often not called "serial". Mark driver-model stdio devices so that they can be detected and we can look up the uclass. This is a more reliable way of finding out whether the console is connected to a serial device or not. Signed-off-by: Simon Glass <sjg@chromium.org>
* | serial: stm32x7: Convert CONFIG_STM32X7_SERIAL to KconfigPatrice Chotard2017-07-311-0/+7
| | | | | | | | | | | | | | Add CONFIG_STM32X7_SERIAL as a Kconfig option. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
* | dm: Kconfig: fix typo in help for SPL_PINCTRLPhilipp Tomsich2017-07-311-1/+1
| | | | | | | | | | | | | | Changes 'controlloers' to 'controllers' in the help-text for SPL_PINCTRL. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | watchdog: Introduce watchdog driver for Intel TangierFelipe Balbi2017-07-303-1/+82
| | | | | | | | | | | | | | | | | | Add watchdog driver for Intel Tangier based platforms. Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge git://git.denx.de/u-boot-socfpgaTom Rini2017-07-296-233/+744
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| * | arm: socfpga: Add FPGA driver support for Arria 10Tien Fong Chee2017-07-262-0/+480
| | | | | | | | | | | | | | | | | | | | | | | | Add FPGA driver support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
| * | drivers: Enable FPGA driver build on SPLTien Fong Chee2017-07-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable FPGA driver build for Arria 10 SPL because FPGA driver is needed by Arria 10 SPL to configure and getting DDR up before loading U-boot into DDR and booting from there. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
| * | kconfig: Convert FPGA_SOCFPGA configuration to KconfigTien Fong Chee2017-07-261-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_FPGA_SOCFPGA Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
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