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* mtd: rpc: Add Renesas RPC Hyperflash driverMarek Vasut2018-04-113-0/+406
| | | | | | | | | Add driver for the RPC block in Hyperflash mode. This driver allows access to a CFI Hyperflash attached to the RPC block and does not support RPC in SPI mode. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* mmc: renesas-sdhi: Wait after reconfiguring pinsMarek Vasut2018-04-111-0/+3
| | | | | | | | | The IP requires some time to recuperate after the IO pin properties were changed. Add a delay to assure this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: matsushita-common: Add missing elseMarek Vasut2018-04-111-1/+1
| | | | | | | | | Fix minor rebase omission, the else was missing which triggered two accesses to the register on 64bit variant of the IP. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: matsushita-common: Wait for command completionMarek Vasut2018-04-112-0/+3
| | | | | | | | | | | Make sure to wait for the command to complete altogether, including the trailing 8 clock cycles. This prevents the driver for accidentally writing the CMD register too fast before the previous command fully completed. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: matsushita-common: Correctly set mode in 16bitMarek Vasut2018-04-111-2/+0
| | | | | | | | | The HOST_MODE register must be set to 0 when the IP is operated in 16bit mode, otherwise 16bit access to the data FIFO may fail. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: matsushita-common: Special case only select registers in 16bitMarek Vasut2018-04-111-1/+3
| | | | | | | | | | | There are only a few registerse used in the 16bit mode which are 32bit internally. Special-case only those in the IO accessors and always write both halves. Any other register access is protected from accidentally overwriting neighboring register. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: renesas-sdhi: Add Renesas SDR104/HS200 tuning supportMarek Vasut2018-04-111-2/+290
| | | | | | | | Add code for PHY tuning required for SDR104/HS200 support on Renesas RCar. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: matsushita-common: Export register access functionsMarek Vasut2018-04-112-2/+6
| | | | | | | | | | Export the matsu_sd_{read,write}l() common register access functions, so that they can be used by other drivers sharing the common code. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: matsushita-common: Properly handle pin voltage configurationMarek Vasut2018-04-112-9/+46
| | | | | | | | | Factor out the regulator handling into set_ios and add support for selecting pin configuration based on the voltage to support UHS modes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: matsushita-common: Always check controller versionMarek Vasut2018-04-111-9/+8
| | | | | | | | | | | Handle the controller version even if quirks are set. The controller in Renesas Gen3 SoCs does provide the version register, which indicates a controller v10 and the controller does support internal DMA and /1024 divider. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: matsushita-common: Handle bus width 0Marek Vasut2018-04-111-0/+1
| | | | | | | | | Handle bus width 0 as 1-bit bus to assure valid content of MATSU_SD_OPTION register WIDTH field. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: matsushita-common: Handle DMA completion flag differencesMarek Vasut2018-04-112-3/+11
| | | | | | | | | | | The DMA READ completion flag position differs on Socionext and Renesas SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on them. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: matsushita-common: Handle Renesas div-by-1Marek Vasut2018-04-112-1/+3
| | | | | | | | | | On the Renesas version of the IP, the /1 divider is realized by setting the clock register [7:0] to 0xff instead of setting bit 10 of the register. Check the quirk and handle accordingly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: matsushita-common: Add Renesas RCar quirksMarek Vasut2018-04-112-18/+30
| | | | | | | | | | Add a quirk to identify that the controller is Renesas RCar variant of the Matsushita SD IP and another quirk indicating it can support Renesas RCar HS200/HS400/SDR104 modes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: matsushita-common: Use mmc_of_parse()Marek Vasut2018-04-111-16/+7
| | | | | | | | Drop the ad-hoc DT caps parsing in favor of common framework function. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: renesas-sdhi: Handle 16bit IPMarek Vasut2018-04-111-0/+13
| | | | | | | | | | | | The Renesas RCar Gen2 chips have a mix of 32bit and 16bit variants of the IP. There is no DT property which allows discerning those, so what Linux does is it checks the size of the register area and if it is 0x100, the IP is 16bit, otherwise the IP is 32bit. Handle the distinction the same way. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: uniphier: Allow passing quirks to the probe functionMarek Vasut2018-04-114-5/+16
| | | | | | | | | | Certain instances of the SD IP require more elaborate digging in the DT to figure out which variant of the SD IP is in use. Allow explicit passing of the quirks into the probe function. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: uniphier: Add support for 16bit variantMarek Vasut2018-04-112-4/+39
| | | | | | | | | | Add support for 16bit mutation of the Matsushita SD IP. Since some registers are internally 32bit, the matsu_sd_{read,write}l() has to special-case this 16bit variant a bit. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: uniphier: Drop useless checkMarek Vasut2018-04-111-8/+2
| | | | | | | | | | Drop useless check in matsu_sd_{read,write}q(), this is only ever called to read the data from FIFO and only when 64bit variant of the block is used anyway. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: uniphier: Factor out FIFO accessorsMarek Vasut2018-04-111-62/+60
| | | | | | | | | | Add macros to generate the FIFO accessors, since the code is almost the same with only minor differences. This is done in preparation for adding 16bit variant of the IP. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: renesas-sdhi: Add Renesas SDHI Kconfig entryMarek Vasut2018-04-112-4/+14
| | | | | | | | | Add Kconfig entry for the Renesas SDHI variant of the controller and split the Makefile entries accordingly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: uniphier: Split out SoC specific bits from the driverMarek Vasut2018-04-115-840/+921
| | | | | | | | | | | | | Factor out common code from the uniphier SD driver, change the prefix of the functions from uniphier_sd_ to matsu_sd_ and create separate renesas-sdhi.c driver. Thus far, all the code is still compiled when CONFIG_UNIPHIER_MMC is selected and there is no functional change. This patch is a preparation for further split of the SoC specific parts of the Matsushita SD driver, used both on Uniphier and R-Car. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* serial: Fix Makefile during SPL and TPL buildMarek Vasut2018-04-111-2/+18
| | | | | | | | | | | | | | | | | This patch fixes a situation where CONFIG_DM_SERIAL is enabled for regular U-Boot and SPL, but not for TPL. In that case, the build will try to include serial-uclass into the TPL nonetheless, because CONFIG_DM_SERIAL is set. The solution is to check if the build is for SPL or TPL and in that case, check if CONFIG_$(SPL_TPL_)DM_SERIAL is also set. Only in that case, include serial-uclass.c . If the build is for regular U-Boot, CONFIG_BUILD is not set, so only check if CONFIG_DM_SERIAL is set and if so, include serial-uclass.c Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
* clk: add sandbox test for bulk APINeil Armstrong2018-04-101-0/+29
| | | | | | | | | | This patch adds the bulk clock API tests for the sandbox test suite. It's very similar to the main test but only uses the _bulk() API and checks if the clocks are correctly enabled/disabled. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: Add get/enable/disable/release for a bulk of clocksNeil Armstrong2018-04-101-0/+59
| | | | | | | | | | | This patch adds a "bulk" API to the clock API in order to get/enable/disable /release a group of clocks associated with a device. This bulk API will avoid adding a copy of the same code to manage a group of clocks in drivers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* reset: add sandbox test for bulk APINeil Armstrong2018-04-102-1/+30
| | | | | | | | | | | | | | This patch adds the bulk reset API tests for the sandbox test suite. Unlike the main test, it also check the "other" reset signal using the bulk API and checks if the resets are correctly asserted/deasserted. To allow the bulk API to work, and avoid changing the DT, the number of resets of the sandbox reset controller has been bumped to 101 for the "other" reset line to be valid. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* reset: Add get/assert/deassert/release for bulk of reset signalsNeil Armstrong2018-04-101-0/+60
| | | | | | | | | | | This patch adds a "bulk" API to the reset API in order to get/deassert/ assert/release a group of reset signals associated with a device. This bulk API will avoid adding a copy of the same code to manage a group of reset signals in drivers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* serial: meson: Update compatible with new Linux bindingsNeil Armstrong2018-04-101-0/+1
| | | | | | | | | | | | The Amlogic Meson SoCs serial bindings were not written when serial support was pushed into Linux and U-Boot. A clean bindings document has been merged into Linux tree to correctly handle the multiple clocks feeding the serial peripheral. This update the U-Boot serial_meson driver with the new compatible string for Amlogic Meson GX Socs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* reset: Add Amlogic Meson Reset ControllerNeil Armstrong2018-04-103-0/+99
| | | | | | | The Amlogic Meson SoCs embeds up to 256 reset lines, add the corresponding driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* sysreset: syscon: convert to use live dtÁlvaro Fernández Rojas2018-04-101-6/+2
| | | | | Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* Merge tag 'xilinx-for-v2018.05-rc2' of git://git.denx.de/u-boot-microblazeTom Rini2018-04-096-18/+66
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx changes for v2018.05-rc2 - Various DT changes and sync with mainline kernel - Various defconfig updates - Add SPL init for zcu102 revA - Add new zynqmp boards zcu100/zcu104/zcu106/zcu111/zc12XX and zc1751-dc3 - Net fixes - xlnx,phy-type - 64bit axi ethernet support - arasan: Fix nand write issue - fpga fixes - Maintainer file updates
| * net: phy: xilinx_phy: Read phytype using property xlnx,phy-typeSiva Durga Prasad Paladugu2018-04-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | This patch reads phytype from property "xlnx,phy-type" instead od simply looking for "phy-type". This is to be inline with Linux and also fixes the issue of detecting it wrongly in u-boot. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * axi: ethernet: Added support for 64 bit addressing for axi-ethernetVipul Kumar2018-04-091-8/+25
| | | | | | | | | | | | | | | | | | This patch uses writeq() function to enable greater than 32 bit addressing of axi-ethernet for the ZynqMP devices. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * nand: arasan_nfc: Fixed NAND write issueVipul Kumar2018-04-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | In commit 2453c695185f ("arm64: zynqmp: nand: Fixed NAND erase issue for size 1GiB or more"), ARASAN_NAND_MEM_ADDR1_PAGE_MASK macro changed to 0xFFFF and the same macro is used in nand write and so that getting nand write error. This patch reverted this macro to the 0xFFFF0000 and used ARASAN_NAND_MEM_ADDR1_COL_MASK in the nand erase function which is equal to 0xFFFF. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * fpga: zynq: Add delay after PCFG_PROG_B changeSiva Durga Prasad Paladugu2018-04-091-0/+16
| | | | | | | | | | | | | | | | | | | | There is delay needed after PCFG_PROGB change if AES key source is efuse. This fixes the issue of encrypted bitstream loading with AES efuse as key source. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * fpga: zynqmp: Fix the nonsecure bitstream loading issueSiva Durga Prasad Paladugu2018-04-091-2/+6
| | | | | | | | | | | | | | | | | | | | Xilfpga library expects the size of bitstream in a pointer but currenly we are passing the size as a value. This patch fixes this issue. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * fpga: zynqmp: Update zynqmp_load() as per latest xilfpgaSiva Durga Prasad Paladugu2018-04-091-5/+1
| | | | | | | | | | | | | | | | | | | | Latest xilfpga expects to set BIT5 of flags for nonsecure bitsream and also expects length in bytes instead of words This patch does the same. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
| * fpga: zynqmp: Add support to get the PCAP status for fpga info commandNitin Jain2018-04-091-0/+14
| | | | | | | | | | | | | | | | | | This patch adds support for ZynqMP platform to print FPGA PCAP status for "fpga status" command. Signed-off-by: Nitin Jain <nitinj@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * clk: zynqmp: Add new compatible string for clock driverMichal Simek2018-04-091-0/+1
| | | | | | | | | | | | New and old clk drivers are sharing IDs and descriptions. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | net: Move enetaddr env access code to env config instead of net configAlex Kiernan2018-04-087-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order that we can use eth_env_* even when CONFIG_NET isn't set, move these functions to environment code from net code. This fixes failures such as: board/ti/am335x/built-in.o: In function `board_late_init': board/ti/am335x/board.c:752: undefined reference to `eth_env_set_enetaddr' u-boot/board/ti/am335x/board.c:766: undefined reference to `eth_env_set_enetaddr' which caters for use cases such as: commit f411b5cca48f ("board: am335x: Always set eth/eth1addr environment variable") when Ethernet is required in Linux, but not U-Boot. Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
* | usb: gadget: USB_ETHER requires network supportAlex Kiernan2018-04-081-0/+1
| | | | | | | | | | | | | | | | In order to compile the USB Ethernet gadget support we require that NET is enabled, add that dependency here. Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Migrate CONFIG_DRIVER_TI_CPSW to KconfigAlex Kiernan2018-04-081-0/+7
|/ | | | | | | This converts CONFIG_DRIVER_TI_CPSW to Kconfig Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* treewide: Migrate CONFIG_FSL_ESDHC to KconfigMario Six2018-04-081-0/+6
| | | | | | Migrate the CONFIG_FSL_ESDHC option to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* treewide: Migrate CONFIG_TSEC_ENET to KconfigMario Six2018-04-081-0/+7
| | | | | | Migrate the CONFIG_TSEC_ENET option to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* Revert "spi: atmel: Drop non-dm code"Tom Rini2018-04-072-0/+217
| | | | | | | | | As we aren't quite able to convert some platforms with a very small size limit in SPL yet, we need to revert this for now. This reverts commit 7b0947787358c6b277431d6b76ce043d8bec641d. Signed-off-by: Tom Rini <trini@konsulko.com>
* Revert "spi: atmel: Drop atmel_spi.h"Tom Rini2018-04-072-88/+93
| | | | | | | | | As we aren't quite able to convert some platforms with a very small size limit in SPL yet, we need to revert this for now. This reverts commit 37434db29be495ef41f204a97b8bf13b1418f97d. Signed-off-by: Tom Rini <trini@konsulko.com>
* gpio: uclass: Fix debug stringMario Six2018-04-061-1/+1
| | | | | | | | A debug string still has the old name of a function being called; update it. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
* watchdog: Fix Kconfig alignment for WDT_SANDBOXMichal Simek2018-04-061-3/+3
| | | | | | | Fix Kconfig alignment which should be <tab><space><space>. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* rtc: rx8025: remove redundant code in rtc_resetChris Packham2018-04-061-17/+1
| | | | | | | | | As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the command "date reset" will set the date/time to 2000-01-01 0:00:00 after calling rtc_reset(). This means that the rx8025 implementation of rtc_reset() does not need to call rtc_set(). Signed-off-by: Chris Packham <judge.packham@gmail.com>
* rtc: rs5c372: remove redundant code in rtc_resetChris Packham2018-04-061-23/+1
| | | | | | | | | As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the command "date reset" will set the date/time to 2000-01-01 0:00:00 after calling rtc_reset(). This means that the rs5c372 implementation of rtc_reset() does not need to call rtc_set(). Signed-off-by: Chris Packham <judge.packham@gmail.com>
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