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* pinctrl: add imx8m driverPeng Fan2019-03-133-0/+51
| | | | | | Add i.mx8m pinctrl driver. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* pinctrl: renesas: r8a77990: Reivse USB ID pin nameHiroyuki Yokoyama2019-03-041-3/+3
| | | | | | | | | Since the datasheet Rev.1.00 has an error about the USB ID pin name, this patch revises it. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit3 when using TX0Hiroyuki Yokoyama2019-03-041-2/+2
| | | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50, the MOD_SEL0 bit3 is set to 0 when TX0_A pin function is selected, and the MOD_SEL0 bit3 is set to 1 when TX0_B pin function is selected. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_NHiroyuki Yokoyama2019-03-041-2/+2
| | | | | | | | | | According to the R-Car Gen3 Hardware Manual Rev.1.50, the MOD_SEL0 bit16 is set to 0 when NFALE_A and NFRB_N_A pin functions are selected. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit2 when using RX2,TX2 and SCK2Hiroyuki Yokoyama2019-03-041-5/+5
| | | | | | | | | | According to the R-Car Gen3 Hardware Manual Rev 1.50, the MOD_SEL0 bit2 is set when RX2_{A,B}, TX2_{A,B} and SCK2_A pin functions are selected. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* pinctrl: renesas: r8a77990: Fix rename RTSx_N_TANS_x to RTSx_N_xHiroyuki Yokoyama2019-03-041-17/+17
| | | | | | | | | | This patch fixes the allocation name "RTSx_N_TANS_x" of IPSR / MOD_SEL0/1 of r8a77990 to "RTSx_N_x". This information was confirmed in the R-Car Gen3 Hardware Manual Rev.1.50. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* pinctrl: renesas: Fix r8a779{6,65} rename sel_ndfc to sel_ndfHiroyuki Yokoyama2019-03-041-11/+11
| | | | | | | | | | This patch fixes the allocation name "sel_ndfc" of MOD_SEL2[22] of r8a7796 / r8a77965 to "sel_ndf". This information was confirmed in the R-Car Gen3 Hardware Manual Rev.1.50. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* pinctrl: renesas: Remove r8a779{5,6,65} CC5_OSCOUT of IP17Hiroyuki Yokoyama2019-03-042-4/+2
| | | | | | | | | | This patch removes CC5_OSCOUT assignment of IP17[3:0] of r8a7795 / r8a7796 / r8a77965. This information was confirmed in the R-Car Gen3 Hardware Manual Rev.1.50. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* pinctrl: renesas: Fix r8a779{5,6,65} rename sel_adg_ to sel_adgHiroyuki Yokoyama2019-03-042-20/+20
| | | | | | | | | | This patch fixes to the correct names, and "_" is not include after "adg" for r8a7795/r8a7796/r8a77965. This information was confirmed in the R-Car Gen3 Hardware Manual Rev.1.50. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* pinctrl: renesas: Fix r8a779{5,6,65} assign to GP7_03/02 of GPSR7Hiroyuki Yokoyama2019-03-042-39/+58
| | | | | | | | | | This patch is change the bit assignment of "HDMI1_CEC" to "GP7_03", and "HDMI0_CEC" to "GP7_02". This information was confirmed in the R-Car Gen3 Hardware Manual Rev.1.50. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* pinctrl: renesas: Drop def_bool per SoCMarek Vasut2019-02-251-10/+0
| | | | | | | | Drop per SoC def_bool on each driver, since this is now implied by SoC Kconfig option instead. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* pinctrl: Kconfig: fix missing include of rockchip/KconfigPhilipp Tomsich2019-02-011-0/+1
| | | | | | | | After the merge of the new, generic pinctrl-code, the include for rockchip/Kconfig was missing. Add it here, so we can select the pinctrl-driver for SPL. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* pinctrl: Kconfig: sort includes alphabeticallyPhilipp Tomsich2019-02-011-5/+5
| | | | | | | | To make adding new subdirectories easier, let's enforce alphabetical ordering of the includes of Kconfig files in the respective subdirectories. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* pinctrl: rockchip: Clean the unused rockchip pinctrl driversDavid Wu2019-02-019-6387/+0
| | | | | | | | | | | If we used the pinctrl-rockchip driver, these code is not needed, so remove them. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* pinctrl: rockchip: Add common rockchip pinctrl driverDavid Wu2019-02-0115-100/+2531
| | | | | | | | | | Use this driver to fit all Rockchip SOCs and to support the desired pinctrl configuration via DTS. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3288: Add i2s pinctrl and clock supportSimon Glass2019-02-011-0/+14
| | | | | | | | Add support for setting pinctrl and clock for I2S on rk3288. This allows the sound driver to operate. These settings were created by rkmux.py Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* Merge tag 'u-boot-imx-20190129' of git://git.denx.de/u-boot-imxTom Rini2019-01-301-1/+2
|\ | | | | | | For 2019.04
| * pinctrl: imx: Fix select input issueYe Li2019-01-281-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinctrl supports to set any bit in input register on iMX6 if the MSB of input value is 0xff. But the driver uses signed int for input value, so when executing the codes below, it won't meet. Because this is arithmetic right shift. if (input_val >> 24 == 0xff) Fix the issue by changing the input_val, config_val and mux_mode to u32. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* | pinctrl: meson: add pinconf supportJerome Brunet2019-01-295-7/+123
|/ | | | | | | | | | | | Adding pinconf support is necessary to enable boot from SPI without breaking the eMMC. When booting from SPI, the ROM code leave pull downs on the eMMC pad. We need to set pinconf provided in DT to solve this Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [narmstrong: added missing comma in pinctrl-meson-axg-pmx.c]
* pinctrl: mscc: Add gpio and pinctrl for Serval SoC family.Horatiu Vultur2019-01-233-0/+244
| | | | | | | | The Serval SoC family has 32 pins. Currently there is no support for Serval in Linux kernel. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* pinctrl: mscc: Add gpio and pinctrl for Servalt SoC family.Horatiu Vultur2019-01-233-0/+279
| | | | | | | | The Servalt SoC family has 36 pins. Currently there is not support for Servalt pinctrl in Linux kernel. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
* pinctrl: Kconfig: spelling fixesChris Packham2019-01-181-1/+1
| | | | | Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pinctrl: mscc: Add gpio and pinctrl for Jaguar2 SOC familyHoratiu Vultur2019-01-167-29/+443
| | | | | | | | The Jaguar2 SOC family has 63 gpio pins therefore I extended mscc-common to support new numbe of pins and remove any platform dependency from mscc-common. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
* Revert "dm: pinctrl: Prevent (re-)configuring pins when already done before ↵Lukasz Majewski2019-01-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | relocation" This reverts commit a7f4b4b344396590845e6552c82829ef68ef9f89. As reported by Alex Kiernan the above optimization introduces a regression in the below use case where: 1. Device has defined 'u-boot,dm-spl' property (@ eMMC DTS node) 2. The device downloads its MLO/SPL via UART (not eMMC - the eMMC pinmux pins are NOT probed/configured in MLO/SPL). 3. The loaded via UART MLO/SPL wants to load Linux from eMMC. In this case the DM core and pinctrl uclass checks 'u-boot,dm-spl' and don't configure pins (as it thinks that those were initialized in MLO/SPL). As we are very close to release - please revert this commit. Reported-by: Alex Kiernan <alex.kiernan@gmail.com> Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3399: fix missing braces in full pinctrlPhilipp Tomsich2019-01-061-2/+3
| | | | | | | | | | | Braces around the error-case for rk3399_pinctrl_set_pin_pupd lead to an unconditional (and unintended) return from the function without it ever setting pin-configurations. Fix it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3399: Add Kconfig option for full pinctrl driverChristoph Muellner2019-01-022-0/+19
| | | | | | | | | | This patch adds a Kconfig option to enable the full pinctrl driver for the RK3399. This flag needs to be enabed in order to get the features of the full pinctrl driver compiled in (i.e. a .set_state() callback). Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3399: Add improved pinctrl driver.Christoph Muellner2019-01-021-0/+227
| | | | | | | | | | | | | | | | | | | | The current pinctrl driver for the RK3399 has a range of qulity issues. E.g. it only implements the .set_state_simple() callback, it does not parse the available pinctrl information from the DTS (instead uses hardcoded values), is not flexible enough to cover devices without 'interrupt' field in the DTS (e.g. PWM), is not written generic enough to make code reusable among other rockchip SoCs... This patch addresses these issues by reimplementing the whole driver from scratch using the .set_state() callback. The new implementation covers all featurese of the old code (i.e. it supports pinmuxing and pullup/pulldown configuration). This patch has been tested on a RK3399-Q7 SoM (Puma). Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* dm: pinctrl: Add pinctrl_decode_pin_config_dm().Christoph Muellner2019-01-021-0/+22
| | | | | | | | | pinctrl_decode_pin_config_dm() is basically a feature-equivalent implementation of pinctrl_decode_pin_config(), which operates on struct udevice devices and uses the dev_read_*() API. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* Merge tag 'u-boot-imx-20190101' of git://www.denx.de/git/u-boot-imxTom Rini2019-01-013-0/+55
|\ | | | | | | | | | | | | | | | | imx for 2019.01 - introduce support for i.MX8M - fix size limit for Vhybrid / pico boards - several board fixes - w1 driver for MX2x / MX5x
| * ARM: vybrid: Provide pinctrl driver for Vybrid (vf610)Lukasz Majewski2019-01-013-0/+55
| | | | | | | | | | | | | | This implementation comply with other iMX devices pinctrl drivers already available in U-boot. Signed-off-by: Lukasz Majewski <lukma@denx.de>
* | dm: pinctrl: Prevent (re-)configuring pins when already done before relocationLukasz Majewski2018-12-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit prevents from re-configuring pins if those were configured before relocation. Some pins - like UART or DDR must be setup before relocation (as they have 'u-boot,dm-pre-reloc' property set in DTS). Without this change, those pins are re-configured after relocation (pre_reloc_only = 0, so we do not "continue"). Such behavior may be a problem for DDR PAD configuration, as they might be already leveled/tuned with original setup). Signed-off-by: Lukasz Majewski <lukma@denx.de>
* | pinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based)Gregory CLEMENT2018-12-198-0/+676
|/ | | | | | | | | | | | | | | | This driver supports the pin and gpio controller found in the Ocelot and Luton SoCs. The driver was inspired from the pinctrl driver in Linux, but was simplified and was modified to allow supporting an other SoCs (Luton). For Ocelot and Luton the controller is the same, only the pins to program differ. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> [changed to only descend into mscc/ dependent on CONFIG_PINCTRL_MSCC] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* Merge tag 'u-boot-amlogic-20181207' of git://git.denx.de/u-boot-amlogicTom Rini2018-12-072-13/+13
|\ | | | | | | | | | | Two fixes for the Amlogic Pinctrl driver : - bad usage of clrsetbits_le32 - bad pin definition for AXG Family
| * pinctrl: meson: axg: Fix GPIO pin offsetsCarlo Caione2018-12-071-11/+11
| | | | | | | | | | | | | | | | | | | | | | The pin number (first and last) in the bank definition is missing the pin base offset shifting. This is causing a miscalculation when retrieving the register and pin offsets in the GPIO driver causing the 'gpio' command to drive the wrong pins / GPIOs in the second GPIO chip (the AO bank is driven correctly because the shifting is already 0). Signed-off-by: Carlo Caione <ccaione@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * pinctrl: meson: Fix GPIO direction registers accessCarlo Caione2018-12-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The macros used to set the direction of the GPIO pins are misused, resulting in a wrong behavior when trying to read the GPIO input level from U-Boot. A better macro is also used when setting the output direction. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev()Patrice Chotard2018-12-071-18/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | pinctrl: stm32: Move gpio_dev list filling outside probe()Patrice Chotard2018-12-071-25/+38
| | | | | | | | | | | | | | Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | pinctrl: stm32: make pinctrl use hwspinlockBenjamin Gaignard2018-12-061-4/+23
|/ | | | | | | | | | | | Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogicTom Rini2018-11-2911-122/+1372
|\ | | | | | | | | | | | | Cleanup and update towards support for Amlogic Meson AXG SoCs : - mmc: meson-gx: Add AXG compatible - net: designware: add meson meson compatibles - Amlogic Meson cleanup for AXG SoC support
| * pinctrl: meson: add axg supportJerome Brunet2018-11-265-0/+1180
| | | | | | | | | | | | | | | | This adds support for the Amlogic AXG SoC pinctrl and GPIO controller using a specific set of pinctrl functions which differs from the GX SoCs. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * pinctrl: meson: select generic pinctrlJerome Brunet2018-11-261-1/+1
| | | | | | | | | | | | | | | | Meson pinctrl needs generic pinctrl, rather than depending on it select it Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * pinctrl: meson: rework gx pmx functionJerome Brunet2018-11-268-121/+191
| | | | | | | | | | | | | | | | | | In preparation of supporting the new Amlogix AGX SoCs, we need to move the Amlogic GX pinmux functions out of the common code to be able to add a different set of SoC specific pinmux functions for AXG. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | pinctrl: MediaTek: add pinctrl driver for MT7623 SoCRyder Lee2018-11-284-0/+1291
| | | | | | | | | | | | | | | | | | | | This patch adds pinctrl support for MT7623 SoC. And most of the structures are used to hold the hardware configuration for each pin. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | pinctrl: MediaTek: add pinctrl driver for MT7629 SoCRyder Lee2018-11-287-0/+1163
|/ | | | | | | | | | | | | | This patch adds pinctrl support for MT7629 SoC. The IO core found on the SoC has the registers for pinctrl, pinconf and gpio mixed up in the same register range. Hence the driver also implements the gpio functionality through UCLASS_GPIO. This also creates a common file as there might be other chips that use the same binding and driver, then being a little more abstract could help in the long run. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pinctrl: sandbox: Add get_pin_muxing ops supportPatrice Chotard2018-11-161-0/+18
| | | | | | | | Add get_pin_mux ops support to display the pin muxing description of the sandbox_pins[] Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pinctrl: stm32: Add get_pin_muxing() opsPatrice Chotard2018-11-161-0/+71
| | | | | | | | Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pinctrl: stm32: Add get_pin_name() opsPatrice Chotard2018-11-161-0/+46
| | | | | | | | Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pinctrl: stm32: Add get_pins_count() opsPatrice Chotard2018-11-161-5/+85
| | | | | | | | | | | | | | | | | | | | Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: pinctrl: Add pinctrl_get_pin_name and pinctrl_get_pins_countPatrice Chotard2018-11-161-0/+23
| | | | | | | | | | Add pinctrl_get_pin_name() and pinctrl_get_pins_count() methods to obtain pin's name and pin's muxing given a pin reference. This will be used by the new pinmux command. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: pinctrl: Add get_pin_muxing() opsPatrice Chotard2018-11-161-0/+11
| | | | | | | | Add get_pin_muxing() which allows to display the muxing of a given pin belonging to a pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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