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* phy: phy-mtk-tphy: make ref clock optionalChunfeng Yun2020-01-161-1/+2
| | | | | | | | | If make the ref clock optional, no need refer to fixed-clock when the ref clock is always on or comes from oscillator directly. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* phy: phy-mtk-tphy: remove the check of -ENOSYSChunfeng Yun2020-01-161-2/+1
| | | | | | | | | No need check -ENOSYS anymore after add dummy_enable() for fixed-clock. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* phy: ti-pipe3: Fix SATA & USB PHY power up sequenceRoger Quadros2019-12-261-17/+19
| | | | | | | | | As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence" in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
* phy: ti-pipe3: improve DPLL stability for SATA & USBRoger Quadros2019-12-261-0/+193
| | | | | | | | | | | | | For increased DPLL stability use the settings recommended in the TRM [1] for PHY_RX registers for SATA and USB. For SATA we need to use spread spectrum settings even though we don't have spread spectrum enabled. The suggested non-spread spectrum settings don't work. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
* phy: ti-pipe3: Introduce mode property in driver dataRoger Quadros2019-12-261-6/+28
| | | | | | | | | | Introduce a mode property in the driver data so that we don't have to keep using "of_device_is_compatible()" throughtout the driver. No functional change. Signed-off-by: Roger Quadros <rogerq@ti.com>
* phy: ti-pipe3: Use TRM recommended settings for SATA DPLLRoger Quadros2019-12-261-7/+7
| | | | | | | | | | | | | | The AM572x Technical Reference Manual, SPRUHZ6H, Revised November 2016 [1], shows recommended settings for the SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings. Use those settings in the driver. The TRM does not show a value for 20MHz SYS_CLK so we use something close to the 26MHz setting. [1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
* drivers: phy: Handle gracefully NULL pointersJean-Jacques Hiblot2019-10-311-5/+25
| | | | | | | For some controllers PHYs can be optional. Handling NULL pointers without crashing nor failing, makes it easy to handle optional PHYs. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
* Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mipsWIP/25Oct2019Tom Rini2019-10-252-68/+158
|\ | | | | | | | | | | | | | | | | - bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC
| * phy: mt76x8-usb-phy: add slew rate calibration and remove non-mt7628 partWeijie Gao2019-10-252-68/+158
| | | | | | | | | | | | | | | | This patch adds slew rate calibration for mt76x8-usb-phy, removes code which belongs to mt7620, and gets rid of using syscon and regmap by using clock driver and reset controller. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* | phy: keystone-usb: handle the transition of the USB power domainJean-Jacques Hiblot2019-10-241-0/+22
|/ | | | | | | | | | There is no proper power domain support for the keystone platforms. However we need to turn off the USB domains before jumping to linux or it fail to boot (observed with k2e and k2l platforms). This can be done in the PHY driver as it is dedicated only to the keystone platforms and matches the required on/off sequence. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
* phy: mediatek: add MediaTek T-PHY support for PCIeRyder Lee2019-10-113-0/+374
| | | | | | | | | | | | The driver provides PHY for USB2, USB3.0, PCIe and SATA, and now we just enable PCIe. As for the other functionalities will be added gradually in upcoming days. This is adapted from the Linux version. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
* Kconfig: Varios: Fix more SPL, TPL dependenciesAdam Ford2019-08-261-1/+1
| | | | | | | | | | | | | | | Several options are presenting themselves on a various boards where the options are clearly not used. (ie, SPL/TPL options when SPL or TPL are not defined) This patch is not attempting to be a complete list of items, but more like low hanging fruit. In some instances, I wasn't sure of DM was required, so I simply made them SPL or TPL. This patch attempts to reduce some of the menuconfig noise by defining dependencies so they don't appear when not used. Signed-off-by: Adam Ford <aford173@gmail.com>
* phy: add support for AM654x SERDESSekhar Nori2019-08-123-0/+421
| | | | | | | | | | | | | | | | | | | | Add a new SERDES driver for TI's AM654x SoC which configures the SERDES only for PCIe. Support fo USB3 can be added later. SERDES in am654x has three input clocks (left input, external reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The driver has support to select PLL mux and left/right output mux as specified in device tree. Signed-off-by: Sekhar Nori <nsekhar@ti.com>
* phy: Add support for phy-da8xx-usbAdam Ford2019-08-083-0/+71
| | | | | | | In preparation for supporting the musb driver, this patch adds support for the usb phy associated with the musb driver. Signed-off-by: Adam Ford <aford173@gmail.com>
* sunxi: phy: Add USB PHY support for Allwinner H6Andre Przywara2019-07-161-0/+20
| | | | | | | | | | | The USB PHY used in the Allwinner H6 SoC has some pecularities (as usual), which require a small addition to the USB PHY driver: In this case the second PHY is PHY3, not PHY1, so we need to skip number 1 and 2 in the code. Just use the respective code from Linux for that. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* phy: meson: add Amlogic G12A USB2 and USB3+PCIE PHY driversNeil Armstrong2019-05-094-0/+570
| | | | | | | | | | | | | | This adds support for the USB PHYs found in the Amlogic G12A SoC Family. The USB2 PHY supports Host and/or Peripheral mode, depending on it's position. The first PHY is only used as Host, but the second supports Dual modes defined by the USB Control Glue HW in front of the USB Controllers. The second driver supports USB3 Host mode or PCIE 2.0 mode, depending on the layout of the board. Selection is done by the #phy-cells, making the mode static and exclusive. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* phy: usbphyc: increase PLL wait timeoutPatrick Delaunay2019-04-211-6/+4
| | | | | | | wait 200us to solve USB init issue on device mode (ums and stm32prog commands) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* phy: usbphyc: move vdda1v1 and vdda1v8 in phy_initPatrick Delaunay2019-04-211-29/+31
| | | | | | | vdda1v1 and vdda1v8 are used by the PLL. Both need to be enabled before starting the PLL. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* phy: usbphyc: Binding update of vdda supplyPatrick Delaunay2019-04-211-24/+30
| | | | | | | Move supply vdda1v1 and vdda1v8 in usbphyc node and no more in port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* phy: usbphyc: update xlate with DT bindingPatrick Delaunay2019-04-211-9/+10
| | | | | | | | | | | | | | | | | | | | | Parameter added for port 1, for example: &usbh_ehci { phys = <&usbphyc_port0>; phy-names = "usb"; vbus-supply = <&vbus_sw>; status = "okay"; }; &usbotg_hs { pinctrl-names = "default"; pinctrl-0 = <&usbotg_hs_pins_a>; phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; status = "okay"; }; Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* phy: usbphyc: remove unused variable indexPatrick Delaunay2019-04-211-2/+0
| | | | | | Remove unused field index in struct stm32_usbphyc_phy. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* phy: Add USB PHY driver for the MT76x8 (7628/7688) SoCStefan Roese2019-04-123-0/+170
| | | | | | | | | | | | | | | | | | | | | | | | This driver is derived from this Linux driver: linux/drivers/phy/ralink/phy-ralink-usb.c The driver sets up power and host mode, but also needs to configure PHY registers for the MT7628 and MT7688. I removed the reset controller handling for the USB host and device, as it does not seem to be necessary right now. The soft reset bits for both devices are enabled by default and testing has shown (with hackish reset handling added), that USB related commands work identical with or without the reset handling. Please note that the resulting USB support is tested only very minimal. I was able to detect one of my 3 currently available USB sticks. Perhaps some further work is needed to fully support the EHCI controller integrated in the MT76x8 SoC. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* phy: Also allow MESON_GXM for MESON_GXL_USB_PHYNeil Armstrong2019-04-031-1/+1
| | | | | | | The MESON_GXL_USB_PHY is also used on the Amlogic Meson GXM SoCs. Fixes: 2960e27e38 ("phy: Add Amlogic Meson USB2 & USB3 Generic PHY drivers") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* phy: sun4i-usb: Use CLK and RESET supportJagan Teki2019-01-181-20/+57
| | | | | | | | | Now clock and reset drivers are available for respective SoC's so use clk and reset ops on phy driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Marek Vasut <marex@denx.de>
* phy: omap_usb2: Add support for am437xJean-Jacques Hiblot2018-12-141-11/+34
| | | | | Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* PHY: Add phy driver for the keystone USB PHYJean-Jacques Hiblot2018-12-143-0/+120
| | | | | Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* phy: Add a new driver for OMAP's USB2 PHYsJean-Jacques Hiblot2018-12-073-0/+206
| | | | | | This drivers supports the USB2 PHY found on omap5 and dra7 SOCs. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
* phy: ti-pip3-phy: Add support for USB3 PHYVignesh R2018-12-071-8/+24
| | | | | | | | | Add support to handle USB3 PHYs present on AM57xx/DRA7xx SoCs. This is needed to move AM57xx to DM_USB. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
* drivers: cosmetic: Convert SPDX license tags to Linux Kernel stylePatrick Delaunay2018-10-281-2/+2
| | | | | | | | | Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* phy: rcar: Add R-Car Gen3 PHY driverMarek Vasut2018-10-033-0/+170
| | | | | | | | | Add a PHY driver for the R-Car Gen3 which allows configuring USB OTG PHY on Gen3 into host mode and toggles VBUS in case a dedicated regulator is present. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* phy: db410c: Add MSM USB PHY driverRamon Fried2018-09-303-0/+118
| | | | | | | | Add a PHY driver for the Qualcomm dragonboard 410c which allows switching on/off and resetting the phy connected to the EHCI controllers and USBHS controller. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
* phy: marvell: add SATA comphy RX/TX polarity invert supportRabeeh Khoury2018-09-192-2/+23
| | | | | | | | | This patch adds support to Armada 7k/8k comphy RX/TX lane swap. The 'phy-invert' DT property defines the inverted signals. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
* phy: marvell: Support changing SERDES map in board fileMarek Behún2018-09-195-16/+18
| | | | | | | | | | | | | | | | | | This adds a weak definition of comphy_update_map to comphy_core, which does nothing. If this function is defined elsewhere, for example in board file, the board file can change some parameters of SERDES configuration. This is needed on Turris Mox, where the SERDES speed on lane 1 has to be set differently when SFP module is connected and when Topaz Switch module is connected. This is a temporary solution. When the comphy driver for armada-3720 will be added to the kernel, the comphy driver in u-boot shall also be updated and this should be done differently then. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
* phy: rcar: Add R-Car Gen2 PHY driverMarek Vasut2018-08-143-0/+199
| | | | | | | | Add a PHY driver for the R-Car Gen2 which allows configuring the mux connected to the EHCI controllers and USBHS controller. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* phy: Fix off-by-one error when parsing DT PHY bindingsMarek Vasut2018-08-141-1/+1
| | | | | | | | | The code fails to copy the last PHY phandle argument, so it is missing from the adjusted phandle args and the consumer cannot use it to determine what the PHY should do. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com>
* phy: sun4i-usb: Update PHY#3 rst_mask only for H3_H5Jagan Teki2018-07-311-3/+2
| | | | | | | | Only H3 and H5 have 4 PHYS so restrict rst_mask only for them by checking PHY id as 3 and update the proper bits. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* phy: sun4i-usb: Remove usb_clk_cfg set in probeJagan Teki2018-07-311-2/+0
| | | | | | | | | usb_clk_cfg is setting CTRL_PHYGATE bit value in probe which is BIT 0 for sun4i, 6i and 8 for a83t but all these were handling in phy ops init exit calls. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* phy: sun4i-usb: Call phy_passby even for PHY#0Jagan Teki2018-07-311-2/+1
| | | | | | | | | | | | | | | On newer Allwinner SoC, there is a pair of EHCI/OHCI USB hosts for OTG host mode. USB PHY passby must be configured for its corresponding PHY. so we can call for PHY#0. on the other hand in past usb-phy code the same thing can be restricted for Lower SoC's, other than H3/H5/A64. Now there is no need to restrict usb passby since the phy driver is DT enabled, and the respective phy calls will trigger based DT information initiated by the drivers. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* phy: Be able to get phy from PHY providerPatrice Chotard2018-07-191-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of phy are provided from a PHY provider nodes as following: usbphyc: usb-phy@5a006000 { compatible = "st,stm32mp1-usbphyc"; reg = <0x5a006000 0x1000>; clocks = <&rcc_clk USBPHY_K>; resets = <&rcc_rst USBPHY_R>; #address-cells = <1>; #size-cells = <0>; usbphyc_port0: usb-phy@0 { reg = <0>; phy-supply = <&vdd_usb>; vdda1v1-supply = <&reg11>; vdda1v8-supply = <&reg18> #phy-cells = <0>; }; usbphyc_port1: usb-phy@1 { reg = <1>; phy-supply = <&vdd_usb>; vdda1v1-supply = <&reg11>; vdda1v8-supply = <&reg18> #phy-cells = <1>; }; }; and PHY are called as following: usbh_ehci: usbh-ehci@5800d000 { compatible = "generic-ehci"; reg = <0x5800d000 0x1000>; clocks = <&rcc_clk USBH>; resets = <&rcc_rst USBH_R>; interrupts = <GIC_SPI 75 IRQ_TYPE_NONE>; companion = <&usbh_ohci>; phys = <&usbphyc_port0>; phy-names = "usb"; status = "okay"; }; generic_phy_get_by_index() must be updated to first look for PHY phandle as previously and in case of error looks for PHY provider by finding the parent's current node which is the PHY provider. args (ofnode_phandle_args struct) must also be updated by inserting the phy index into the PHY provider as args[0]. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2018-06-043-0/+594
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| * phy: sun4i-usb: Add a sunxi specific function for setting squelch-detectJagan Teki2018-05-281-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | The sunxi otg phy has a bug where it wrongly detects a high speed squelch when reset on the root port gets de-asserted with a lo-speed device. The workaround for this is to disable squelch detect before de-asserting reset, and re-enabling it after the reset de-assert is done. Add a sunxi specific phy function to allow the sunxi-musb glue to do this. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
| * phy: sun4i-usb: Add A23 USB PHY configJagan Teki2018-05-281-0/+9
| | | | | | | | | | | | | | Allwinner A23 has 2 USB PHY's and 0x04 has phy ctrl offset. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
| * phy: sun4i-usb: Add A33 USB PHY configJagan Teki2018-05-281-0/+10
| | | | | | | | | | | | | | Allwinner A33 has 2 USB PHY's and 0x10 has phy ctrl offset. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
| * phy: sun4i-usb: Add A31 PHY configJagan Teki2018-05-281-0/+10
| | | | | | | | | | | | | | Allwinner A31 has 3 USB PHY's and rest similar to A10. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
| * phy: sun4i-usb: Add A10/A13/A20 PHY configJagan Teki2018-05-281-0/+28
| | | | | | | | | | | | | | Add PHY configs for Allwinner A10/A13/A20 which are SUN4I. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
| * phy: sun4i-usb: Add A83T USB PHY configJagan Teki2018-05-281-17/+68
| | | | | | | | | | | | | | | | | | Unlike, other Allwinner SUN4I Phy supporting SOC, A83T has 2 USB PHY's and second one is HSIC. So phy control need to configure to handle these HSIC and SIDDQ requirement. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
| * phy: sun4i-usb: Add V3S PHY configJagan Teki2018-05-281-0/+11
| | | | | | | | | | | | | | V3S has 1 USB PHY, rest are similar to A64. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
| * phy: sun4i-usb: Add H3/H5 PHY configJagan Teki2018-05-281-0/+11
| | | | | | | | | | | | | | H3/H5 has 4 USB PHY, rest are similar to A64. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
| * phy: sun4i-usb: Add id_detect and vbus_detect opsJagan Teki2018-05-281-0/+39
| | | | | | | | | | | | | | | | ID and VBUS detection code require when musb changing between Host and/or Peripheral modes. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
| * phy: Add Allwinner A64 USB PHY driverJagan Teki2018-05-283-0/+419
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB PHY implementation for Allwinner SOC's can be handling in to single driver with different phy configs. This driver handle all Allwinner USB PHY's start from 4I to 50I(except 9I). Currently added A64 compatibility more will add in next coming patches. Current implementation is unable to get pinctrl, clock and reset details from DT since the dm code on these will add it future. Driver named as phy-sun4i-usb.c since the same PHY logic work for all Allwinner SOC's start from 4I to A64 except 9I with different phy configurations. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
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