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path: root/drivers/pci
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* dm: pci: Update uclass to support livetreeSimon Glass2017-06-011-14/+12
| | | | | | | Update the PCI uclass to support livetree. This mostly involves fixing the address decoding from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Rename dev_addr..() functionsSimon Glass2017-06-011-2/+2
| | | | | | | | | | | | | | | | | | | These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-05-263-4/+13
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| * armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC supportPriyanka Jain2017-05-233-4/+13
| | | | | | | | | | | | | | | | | | | | | | The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | x86: pci: Allow conditionally run VGA rom in S3Bin Meng2017-05-171-0/+14
|/ | | | | | | | | Introduce a new CONFIG_S3_VGA_ROM_RUN option so that U-Boot can bypass executing VGA roms in S3. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* pci: avoid memory leakxypron.glpk@gmx.de2017-05-121-0/+1
| | | | | | | | | | | strdup uses malloc to allocate memory for str. If we cannot bind to the generic driver we should release the memory. The problem was indicated by clang scan-build. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* fix: mvebu: pcie_dw: Allow probing empty PCIe slotsKonstantin Porotchkin2017-05-091-5/+5
| | | | | | | | | | | | | | | This patch allows probing all PCIe nodes defined in DTS even if there no device connected to such node (no link). Without this fix the driver returns -ENODEV when the PCIe link is down. As result the pci_init function stops scanning bus on first empty PCIe slot and all devices located in higher numbered buses are not discovered. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* Merge git://git.denx.de/u-boot-dmTom Rini2017-04-041-2/+3
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| * pci: correct a function descriptionHou Zhiqiang2017-03-261-2/+3
| | | | | | | | | | | | | | | | | | In the description of function pci_match_one_id(), there are some problems on arguments list and return value description, so correct them. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | pcie-layerscape: Fixup iommu-map property of pci nodeBharat Bhushan2017-03-281-0/+55
| | | | | | | | | | | | | | | | | | This patch fixup iommu-map property on pci node to have a valid mapping of requester-id to stream-id. The requester-id to stream-id mapping is based on PCI-LUT table initialization. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | pcie-layerscape: Initialize pci-lut for NXP chasis-2 socsBharat Bhushan2017-03-281-2/+2
| | | | | | | | | | | | | | | | Layerscape Chasis-2 also uses same PCIe controller as Chasis-3 and have similar PCI-Lut. Signed-off-by: Bharat Bhushan <bharat.bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | pci: layerscape: Fixup device tree node for ls2088aHou Zhiqiang2017-03-281-11/+24
| | | | | | | | | | | | | | | | LS2088A and its variants have different PCIe node than LS2080A. The compatible string is updated accordingly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | pci: layerscape: add LS2088A series SoC pcie supportHou Zhiqiang2017-03-282-0/+43
| | | | | | | | | | | | | | | | The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | pci: layerscape: enable PCIe config readyHou Zhiqiang2017-03-282-0/+9
|/ | | | | | | | | | | In EP mode, to enable accesses from the Root Complex, the CONFIG_READY bit must be set, otherwise any config attempts from the Root Complex will be returned with config retry status (CRS). Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* mvebu: pcie: Add support for GPIO reset for PCIe deviceKonstantin Porotchkin2017-03-231-0/+20
| | | | | | | | | | | | | | | | Add support for "marvell,reset-gpio" property to mvebu DW PCIe driver. This option is valid when CONFIG_DM_GPIO=y Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* dm: core: Replace of_offset with accessorSimon Glass2017-02-084-7/+8
| | | | | | | | | At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Don't try to run the VGA BIOS in 64-bit modeSimon Glass2017-02-061-1/+1
| | | | | | | This is not supported, so disable it for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: mvebu: Fix Armada 38x supportDirk Eibach2017-02-011-12/+13
| | | | | | | | | | | | Armada 38x has four PCI ports, not three. The optimization in pci_init_board() seems to assume that every port has three lanes. This is obviously wrong, and breaks support for Armada 38x. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge git://git.denx.de/u-boot-mpc85xxTom Rini2017-01-251-0/+7
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| * mpc85xx: pcie: Implement workaround for Erratum A007815Tony O'Brien2017-01-241-0/+7
| | | | | | | | | | | | | | | | | | | | | | The read-only-write-enable bit is set by default and must be cleared to prevent overwriting read-only registers. This should be done immediately after resetting the PCI Express controller. Reviewed-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz> [York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
* | Drop CONFIG_WINBOND_83C553Simon Glass2017-01-252-207/+0
|/ | | | | | This is not used in U-Boot. Drop this option and associated dead code. Signed-off-by: Simon Glass <sjg@chromium.org>
* kconfig: move FSL_PCIE_COMPAT to platform KconfigHou Zhiqiang2017-01-181-4/+4
| | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* pci: layerscape: remove unnecessary legacy codeMinghuan Lian2017-01-183-716/+1
| | | | | | | | | | All Layerscape SoCs have supported new PCIe driver based on DM. The lagecy PCIe driver code is unused and can be removed. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* pci: layerscape: add pci driver based on DMMinghuan Lian2017-01-184-0/+754
| | | | | | | | | | | | | There are more than five kinds of Layerscape SoCs. unfortunately, PCIe controller of each SoC is a little bit different. In order to avoid too many macro definitions, the patch addes a new implementation of PCIe driver based on DM. PCIe dts node is used to describe the difference. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* pci: layerscape: move kernel DT fixup to a separate fileHou Zhiqiang2017-01-184-311/+343
| | | | | | | | | To make the layerscape pcie driver clear, move the kernel DT fixup code from pcie_layerscape.c to pcie_layerscape_fixup.c. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* dm: pci: remove pci_bus_to_hose(0) callingMinghuan Lian2017-01-181-10/+7
| | | | | | | | | | | | | | There may be multiple PCIe controllers in a SoC. It is not correct that always calling pci_bus_to_hose(0) to get the first PCIe controller for the PCIe device connected other controllers. We just remove this calling because hose always point the correct PCIe controller. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
* dm: pci: return the real controller in pci_bus_to_hose()Minghuan Lian2017-01-181-1/+1
| | | | | | | | | | | | | for the legacy PCI driver, the function pci_bus_to_hose() returns the real PCIe controller. To keep consistency, this function is changed to return the PCIe controller pointer of the root bus instead of the current PCIe bus. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
* pci: kconfig: fix spelling in descriptionMarcel Ziswiler2017-01-031-1/+1
| | | | | | | Fix 'driver model' rather than 'driver mode' in description. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* pci: mvebu: Add PCIe driver for Armada-8KShadi Ammouri2016-12-053-0/+546
| | | | | | | | | | | | | | | | | | | | | | | This patch adds a driver for the PCIe controller integrated in the Marvell Armada-8K SoC. This controller is based on the DesignWare IP core. The original version was written by Shadi and Yehuda. I ported this driver to the latest mainline U-Boot version with DM support. Tested on the Marvell DB-88F8040 Armada-8K eval board. Signed-off-by: Shadi Ammouri <shadi@marvell.com> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* pci: sh7751: map PCI memory space into SDRAMVladimir Zapolskiy2016-12-021-6/+4
| | | | | | | | | | | | | For ease of use and accounting a condition that on SH4 pci_phys_to_bus() and pci_bus_to_phys() are one in one mappings due to unimplemented __iomem() conversion, this change fixes access to SDRAM memory by PCI devices. This change also generalizes PCI system memory configuration, which is taken from board specific defines rather than hardcoded in the PCI host driver. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* pci: sh7751: fix up PCI I/O space addressVladimir Zapolskiy2016-12-021-1/+1
| | | | | | | | | | | | The change actually maps PCI I/O window to the same address on PCI bus as it is stated by a comment, before the change transfers to the PCI I/O space are failed due to misconfiguration of the most significant 14 bits of the PCI address in PCIIOBR (note that it is set to 0x0). Most probably the problem remained unnoticed, because communcation to all tested PCI devices is done over PCI memory space only. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* pci: Move CONFIG_PCI_PNP to KconfigBin Meng2016-10-281-0/+7
| | | | | | | | | | Introduce CONFIG_PCI_PNP in Kconfig and move over boards' defconfig to use that. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Re-generate configs and include/configs/ changes] Signed-off-by: Tom Rini <trini@konsulko.com>
* drivers/pci/Kconfig: Add PCITom Rini2016-10-271-2/+10
| | | | | | | Add 'PCI' as a menu option and migrate all existing users. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* libfdt: Sync fdt_for_each_subnode() with upstreamSimon Glass2016-10-131-1/+1
| | | | | | | | | | | The signature for this macro has changed. Bring in the upstream version and adjust U-Boot's usages to suit. Signed-off-by: Simon Glass <sjg@chromium.org> Update to drivers/power/pmic/palmas.c: Signed-off-by: Keerthy <j-keerthy@ti.com> Change-Id: I6cc9021339bfe686f9df21d61a1095ca2b3776e8
* vbe: Make vbe_setup_video_priv() publicBin Meng2016-10-121-3/+3
| | | | | | | vbe_setup_video_priv() might be useful to other drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: video: Output verbose information in vbe_setup_video()Bin Meng2016-10-121-1/+8
| | | | | | | | With DM conversion, information like "Video: 1024x768x16" is not shown anymore. Now add these verbose output back. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: video: Add driver-model support to vesa graphicsSimon Glass2016-10-111-0/+55
| | | | | | | | | | Provide a function to run the Vesa BIOS for a given PCI device and obtain the resulting configuration (e.g. display size) for use by the video uclass. This makes it easier to write a video driver that uses vesa and supports driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-231-1/+1
| | | | | | | | | | | Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
* pci: Flip condition for detecting non-PCI parent devicesPaul Burton2016-09-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In pci_uclass_pre_probe an attempt is made to detect whether the parent of a device is a PCI device and that the device is thus a bridge. This was being done by checking whether the parent of the device is of the UCLASS_ROOT class. This causes problems if the PCI controller is a child of some other non-PCI node, for example a simple-bus node. For example, if the device tree contains something like the following then pci_uclass_pre_probe would incorrectly believe that the PCI controller is a bridge, with a PCI parent: / { some_child { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <>; pci_controller: pci@10000000 { compatible = "my-pci-controller"; device_type = "pci"; reg = <0x10000000 0x2000000>; }; }; }; Avoid this incorrect detection of bridges by instead checking whether the parent devices class is UCLASS_PCI and treating a device as a bridge when this is true, making use of device_is_on_pci_bus to perform this test. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pci: xilinx: Add a driver for Xilinx AXI to PCIe bridgePaul Burton2016-09-213-0/+228
| | | | | | | | | | This patch adds a driver for the Xilinx AXI bridge for PCI express, an IP block which can be used on some generations of Xilinx FPGAs. This is mostly a case of implementing PCIe ECAM specification, but with some quirks about what devices are valid to access. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pci: tegra: port to standard clock/reset/pwr domain APIsStephen Warren2016-08-152-5/+159
| | | | | | | | | | | | | Tegra186 supports the new standard clock, reset, and power domain APIs. Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so that it can operate with either set of APIs. On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming. Consequently, this logic is disabled too. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-07-282-1/+5
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| * pci: allow disabling of pci init/enum via envTim Harvey2016-07-281-0/+4
| | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * pcie_imx: increment timeout for link upStefano Babic2016-07-121-1/+1
| | | | | | | | | | | | | | On some boards, the current 20ms timeout is hit. Increase it to 40mS. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | dm: Use dm_scan_fdt_dev() directly where possibleSimon Glass2016-07-272-21/+4
| | | | | | | | | | | | | | Quite a few places have a bind() method which just calls dm_scan_fdt_dev(). We may as well call dm_scan_fdt_dev() directly. Update the code to do this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: Convert users from dm_scan_fdt_node() to dm_scan_fdt_dev()Simon Glass2016-07-272-12/+2
| | | | | | | | | | | | | | This new function is more convenient for callers, and handles pre-relocation situations automatically. Signed-off-by: Simon Glass <sjg@chromium.org>
* | pci: Add board_ prefix to should_load_oprom() and make it weakBin Meng2016-07-121-2/+2
| | | | | | | | | | | | | | | | | | For consistency with board_should_run_oprom(), do the same to should_load_oprom(). Board support codes can provide this one to override the default weak one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | pci: Make load_oprom and run_oprom independentBin Meng2016-07-121-4/+1
| | | | | | | | | | | | | | | | | | At present should_load_oprom() calls board_should_run_oprom() to determine whether oprom should be loaded. But sometimes we just want to load oprom without running. Make them independent. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | pci: Remove CONFIG_ALWAYS_LOAD_OPROMBin Meng2016-07-121-2/+0
|/ | | | | | | This option is defined at nowhere. Remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pci: tegra: actually program REFCLK_CFG* on recent SoCsStephen Warren2016-07-051-9/+10
| | | | | | | | | | | | | | | On recent SoCs, tegra_pcie_phy_enable() isn't called; but instead tegra_pcie_enable_controller() calls tegra_xusb_phy_enable(). However, part of tegra_pcie_phy_enable() needs to happen in all cases. Move that code to tegra_pcie_port_enable() instead. For reference, NVIDIA's downstream Linux kernel performs this operation in tegra_pcie_enable_rp_features(), which is called immediately after tegra_pcie_port_enable(). Since that function doesn't exist in the U-Boot driver, we'll just add it to the tail of tegra_pcie_port_enable() instead. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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