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path: root/drivers/net/zynq_gem.c
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* zynq-gem: Use appropriate cache flush/invalidate for RX and TXStefan Theil2019-01-241-5/+6
| | | | | | | | | | | | | The cache was only flushed before *transmitting* packets, but not when receiving them, leading to an issue where new packets were handed to the receive handler with old contents in cache. This only happens when a lot of packets are received without sending packages every now and then. Also flushing the receive buffers in the transmit function makes no sense and can be removed. Signed-off-by: Stefan Theil <stefan.theil@mixed-mode.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: Add check for 64-bit dma support by hardwareSiva Durga Prasad Paladugu2018-12-031-1/+23
| | | | | | | | | | | This patch throws an error if 64-bit support is expected but DMA hardware is not capable of 64-bit support. It also prints a debug message if DMA is capable of 64-bit but not using it. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
* net: zynq_gem: Added 64-bit addressing supportVipul Kumar2018-12-031-9/+54
| | | | | | | | | | | This patch adds 64-bit addressing support for zynq gem. This means it can perform send and receive operations on 64-bit address buffers. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
* net: gem: Do not setup any clock for Xilinx SoC VersalMichal Simek2018-10-161-0/+4
| | | | | | | Xilinx SoC Versal is using fixed clock where setting rate is not supported. That's why workaround the driver till real clock driver is supported. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: Add support for fixed-link phyMichal Simek2018-09-271-8/+9
| | | | | | | | Based on dt-specs fixed-link doesn't require phy-handle to be used. Fix driver to only read phy related setting when phy-handle is found. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq_gem: Fix reading of max-speed propertySiva Durga Prasad Paladugu2018-09-261-1/+2
| | | | | | | | | | max-speed property is part of phynode and it has to be read using ofnode_read_u32_default(). This fixes the issue of incorrect max-speed read from DT. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: convert to use livetreeSiva Durga Prasad Paladugu2018-07-261-16/+14
| | | | | | | | This patch updates the zynq gem driver to support livetree. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* drivers: net: zynq_gem: fix phy dt node settingGrygorii Strashko2018-07-261-1/+1
| | | | | | | | | | Now zynq_gem driver will overwrite UCLASS_ETH node when PHY is connected and configured which is not correct. Use struct phydev->node instead. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
* net: zynq_gem: Initialize val variable in zynq_gem_miiphy_read()Michal Simek2018-07-021-1/+1
| | | | | | | | phyread can timeout and val will contain random value. Initialize it to zero not to report random value in case of error. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: gem: Check return value from memalign/mallocMichal Simek2018-06-131-0/+6
| | | | | | | | Functions can return NULL in case of error that's why checking return value is needed. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq_gem: Initialize phyreg variableMichal Simek2018-06-131-1/+1
| | | | | | | | | In case of phyread()/phy_setup_op() timeout code is working with uninitialized phyreg variable. Initialize this variable to make sure that code it not working with random value. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq_gem: Fix return type for phy...()Michal Simek2018-06-131-4/+4
| | | | | | | | wait_for_bit_le32 returns negative value on failure. Fix phy...() to handle these failures properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-071-2/+1
| | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
* net: zynq_gem: Use max-speed property from dtSiva Durga Prasad Paladugu2018-04-131-0/+9
| | | | | | | | | | Add support to use max-speed property from dt for determining the supported speed. Use 1000Mbps as default. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq_gem: Dont run any phy detection logic for GMII caseSiva Durga Prasad Paladugu2018-03-231-1/+2
| | | | | | | | | | | | | | This patch bypasses phy detection logic for GMII interface and just depend on phy address received from DT. This patch is required as phy detection logic is different for some phys like xilinx phy which can be connected over SGMII and GMII interface. This fixes the issue of ethernet failures when xilinx phy is connected over GMII interface. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* wait_bit: use wait_for_bit_le32 and remove wait_for_bitÁlvaro Fernández Rojas2018-01-241-6/+6
| | | | | | | | wait_for_bit callers use the 32 bit LE version Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* net: zynq_gem: Dont enable SGMII and PCS selectionSiva Durga Prasad Paladugu2017-11-291-1/+10
| | | | | | | | | Dont enable SGMII and PCS selection if internal PCS/PMA is not used, by getting the info about internal/external PCS/PMA usage from dt property "is-internal-phy". Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: Dont flush dummy descriptorsSiva Durga Prasad Paladugu2017-06-021-4/+0
| | | | | | | | | | Dont flush dummy descriptors as they are already allocated from a region with dcache off. Tested this on Zynq(zc702) and ZynqMP(zcu102) boards. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq_gem: Use wait_for_bit with non breakableSiva Durga Prasad Paladugu2017-06-021-2/+2
| | | | | | | | | | | | Use wait_for_bit to be non breakable as using it with breakable causes issue of un interruptible auto negotiation. This is due to the ctrlc pressed will taken for wait_for_bit() abort during phy_read() and hence not coming out of auto negotiation. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq_gem: Do not return -ENOSYS on successOlliver Schinagl2017-06-021-5/+3
| | | | | | | | | | | | | The .read_rom_hwaddr net_ops hook does not check the return value, which is why it was never caught that we are currently returning 0 if the read_rom_hwaddr function return -ENOSYS and -ENOSYS otherwise. In this case we can simplify this by just returning the result of the function. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* dm: Rename dev_addr..() functionsSimon Glass2017-06-011-1/+1
| | | | | | | | | | | | | | | | | | | These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge tag 'xilinx-for-v2017.05' of git://www.denx.de/git/u-boot-microblazeTom Rini2017-03-161-18/+11
|\ | | | | | | | | | | | | Xilinx changes for v2017.05 - Move to DM clk driver - Add clk support for zynq_sdhci
| * zynq: Move zynq to clock frameworkStefan Herbrechtsmeier2017-02-171-9/+0
| | | | | | | | | | | | | | | | Move the zynq to clock framework and remove unused functions as well as the CONFIG_ZYNQ_PS_CLK_FREQ configuration. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: zynq: Add clk framework support to zynq ethernet driverStefan Herbrechtsmeier2017-02-171-7/+15
| | | | | | | | | | | | | | | | | | If available use the clock framework to set the tx clock rate of the zynq ethernet controller. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: zynq: Don't overwrite gem_rclk_ctrl with default valueStefan Herbrechtsmeier2017-02-171-11/+5
| | | | | | | | | | | | | | | | | | | | The gem[0-1]_rclk_ctrl registers control the source of the rx clock, control and data signals and configure via ps7_init function. Don't overwrite the register with the default value. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | net: zynq_gem: Fix masking of supported phydev featuresNathan Rossi2017-03-071-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | When the zynq_gem driver initializes the phy it sets the supported features that the phy can support and advertise. However instead of masking the supported features such that it limits the available features it sets the phy to have the exact supported features of the zynq_gem. This is problematic as it will enable features that a phy does not have or cannot advertise. Specifically this appears as an issue when using a phy that is only capable of 10/100, but the zynq_gem driver will override this and try to enable and advertise 10/100/1000. Reported-by: Arno Steffens <star@gmx.li> Fixes: 80243528ef ("net: gem: Fix gem driver on 1Gbps LAN") Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Tested-by: Arno Steffens <star@gmx.li> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* dm: core: Replace of_offset with accessorSimon Glass2017-02-081-5/+6
| | | | | | | | | At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
* net: zynq_gem: Use clock driver for ZynqMPSiva Durga Prasad Paladugu2017-01-101-0/+18
| | | | | | | | | Enable and use the clock driver routine defined in clock driver toset required clock appropriately. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: gem: Use wait_for_bit() instead of private mdio_wait()Michal Simek2017-01-101-23/+9
| | | | | | | Using generic wait_for_bit() implementation instead of using private wait function. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: xilinx: Use mdio_register_seq() to support multiple instancesMichal Simek2016-12-201-2/+1
| | | | | | | | | | | | axi_emac, emaclite and gem have the same issue with registering multiple instances with mdio busses. mdio bus name has to be uniq but drivers are setting up only one name for all. Use mdio_register_seq() and pass dev->seq number to allow multiple mdio instances registration. Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Revert "Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze"Tom Rini2016-12-091-1/+2
| | | | | This reverts commit 3edc0c252257e4afed163a3a74aba24a5509b198, reversing changes made to bb135a0180c31fbd7456021fb9700b49bba7f533.
* net: xilinx: Use mdio_register_seq() to support multiple instancesMichal Simek2016-12-081-2/+1
| | | | | | | | | | | | | axi_emac, emaclite and gem have the same issue with registering multiple instances with mdio busses. mdio bus name has to be uniq but drivers are setting up only one name for all. Use mdio_register_seq() and pass dev->seq number to allow multiple mdio instances registration. Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Series-to: u-boot Series-cc: Phani Kiran Kara <phanikiran.kara@gmail.com>
* common: miiphyutil: Work and report phy address in hex in mdio cmdMichal Simek2016-12-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It is confusing that mdio commands work and report phy id as decimal value when mii is working with hex values. For example: ZynqMP> mdio list gem: 21 - TI DP83867 <--> ethernet@ff0e0000 ZynqMP> mdio read ethernet@ff0e0000 0 Reading from bus gem PHY at address 21: 0 - 0x1140 ZynqMP> mii dump 21 0 Incorrect PHY address. Range should be 0-31 ... ZynqMP> mii dump 15 0. (1140) -- PHY control register -- (8000:0000) 0.15 = 0 reset U-Boot normally takes hex values that's why this patch is changing mdio command to handle hex instead of changing mii command to handle decimal values. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq_gem: Correct SGMII enable bit settingSiva Durga Prasad Paladugu2016-11-151-1/+1
| | | | | | | | | Correct the SGMII enable bit position to 27 instead of 31. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq_gem: Modify the nwcfg bit definitionsSiva Durga Prasad Paladugu2016-11-151-8/+8
| | | | | | | | | Modify the nwcfg bit definitions to have 32-bit by removing the extra nibble. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* treewide: replace #include <asm-generic/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-231-1/+1
| | | | | | | | | | | | | | Now, include/linux/errno.h is a wrapper of <asm-generic/errno.h>. Replace all include directives for <asm-generic/errno.h> with <linux/errno.h>. <asm-generic/...> is supposed to be included from <asm/...> when arch-headers fall back into generic implementation. Generally, they should not be directly included from .c files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Add drivers/usb/host/xhci-rockchip.c] Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-05-241-5/+9
|\ | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: drivers/net/zynq_gem.c
| * net: zynq_gem: Add the passing of the phy-handle nodeDan Murphy2016-05-241-5/+10
| | | | | | | | | | | | | | | | | | | | Add the ability to pass the phy-handle node offset to the phy driver. This allows the phy driver to access the DT subnode's data and parse accordingly. Signed-off-by: Dan Murphy <dmurphy@ti.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | phy: Wire return value from phy_config()Michal Simek2016-05-241-2/+1
| | | | | | | | | | | | Fix zynq_gem driver to handle error from phy_config correctly. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | net: xilinx: Handle error value from phy_startup()Michal Simek2016-05-241-1/+4
|/ | | | | | | Handle error returned by phy_startup() properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* net: zynq_gem: Add SGMII support for zynqMPSiva Durga Prasad Paladugu2016-04-041-2/+11
| | | | | | | | | PCS auto negotaiation bit should be enabled along with SGMII autonegotation enabled in phy. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: Return error incase of invalid phy addressSiva Durga Prasad Paladugu2016-04-041-3/+1
| | | | | | | | Return error from probe in case of invalid phy address. This fixes the issue of uboot crash if phy is not detected. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: gem: Allow to set the MAC from an EEPROMJoe Hershberger2016-04-041-0/+18
| | | | | | | | | | Provide board specific option how to read MAC address from ROM. Do it in generic way to be reusable by differnet boards. If this is not enough board specific functions can be created. Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: Add support for SGMII interfaceSiva Durga Prasad Paladugu2016-04-041-7/+19
| | | | | | | | Add support of SGMII interface for zynq GEM. Read xlnx,emio property from DT. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq: Change MDC setup for arm64Michal Simek2016-01-271-0/+4
| | | | | | | | | MDC setting depends on pclk input clocks which varies across SoC. This driver is used by xilinx zynq and zynqmp SOC. Input clock frequence on silicon is 125MHz where divider 64 put frequency below 2.5MHz requires by spec (125/64=1.95). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: Use shared wait_for_bitMateusz Kulikowski2016-01-251-33/+2
| | | | | Use existing library function to poll bit(s). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
* net: gem: Add driver dependencies to PHYLIBMichal Simek2015-12-181-4/+0
| | | | | | | Clear driver dependecies via Kconfig. Remove PHYLIB dependency from the driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: gem: Separate recv and free_pkt functionsMichal Simek2015-12-181-20/+32
| | | | | | | | Use core to call net_process_received_packet() instead of call inside the driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: gem: Fix return value from recvMichal Simek2015-12-181-1/+1
| | | | | | | | recv function should return 0 instead of frame_len not to proceed the same packet again in core. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: gem: Setup default phy address to -1Michal Simek2015-12-181-1/+2
| | | | | | | Undefined phy address is -1 not 0. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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