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* socfpga: stratix10: fix sdram_calculate_sizeDalon Westergreen2018-09-151-2/+2
* drivers/ddr/fsl: fix '__hwconfig without a buffer' messagesJeremy Gebben2018-07-261-8/+6
* ddr: altera: Add ECC DRAM scrubbing support for Arria10Marek Vasut2018-07-121-0/+27
* ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10Marek Vasut2018-07-121-25/+0
* ddr: altera: stratix10: Add DDR support for Stratix10 SoCLey Foon Tan2018-07-122-0/+389
* SPDX: Fixup SPDX tags in a few new filesTom Rini2018-05-201-2/+1
* configs: Add DDR Kconfig support for Arria 10Tien Fong Chee2018-05-181-1/+1
* ARM: socfpga: Add DDR driver for Arria 10Tien Fong Chee2018-05-182-0/+742
* ARM: socfpga: Rename the gen5 sdram driver to more specific nameTien Fong Chee2018-05-182-1/+1
* ARM: mvebu: a38x: Add missing SPDX license identfierChris Packham2018-05-151-1/+3
* ARM: mvebu: a38x: use non-zero size for ddr scrubbingChris Packham2018-05-143-1/+5
* ARM: mvebu: a38x: restore support for setting timingChris Packham2018-05-144-5/+17
* ARM: mvebu: a38x: sync ddr training code with upstreamChris Packham2018-05-1451-5087/+7879
* ARM: mvebu: a38x: remove some unused codeChris Packham2018-05-147-794/+0
* ARM: mvebu: a38x: move sys_env_device_rev_getChris Packham2018-05-141-24/+0
* ARM: mvebu: a38x: move definition of PEX_CFG_DIRECT_ACCESSChris Packham2018-05-141-2/+0
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-0790-185/+90
* Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini2018-04-272-4/+0
* Revert "drivers/ddr/fsl: Dual-license DDR driver"Tom Rini2018-02-1417-17/+17
* drivers/ddr/fsl: Dual-license DDR driverYork Sun2018-02-0917-17/+17
* drivers/ddr/fsl: Cleanup unused variableYork Sun2018-01-305-5/+0
* drivers/ddr/fsl: Modify binding registers to save time on data initYork Sun2018-01-301-11/+49
* drivers/ddr/fsl: Add calculation of register control wordsYork Sun2018-01-303-7/+48
* drivers/ddr/fsl: Add 3DS RDIMM supportYork Sun2018-01-305-14/+80
* drivers/ddr/fsl: Fix workaround for A009803York Sun2018-01-301-1/+1
* drivers/ddr/fsl: Fix DDR4 RDIMM supportYork Sun2018-01-303-22/+40
* Merge git://git.denx.de/u-boot-socfpgaTom Rini2018-01-271-4/+4
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| * ddr: altera: silence PHY calibration unless in debug modeGoldschmidt Simon2018-01-251-4/+4
* | Merge git://git.denx.de/u-boot-spiTom Rini2018-01-261-4/+4
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| * wait_bit: use wait_for_bit_le32 and remove wait_for_bitÁlvaro Fernández Rojas2018-01-241-4/+4
* | ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCsRajesh Bhagat2018-01-231-1/+3
* | ddr: marvell: update ddr controller init and freqChris Packham2018-01-193-21/+34
* | ddr: marvell: update additional ODT settingChris Packham2018-01-191-8/+14
* | ddr: marvell: use correct TREFI valueChris Packham2018-01-191-1/+1
* | ddr: marvell: only assert M_ODT[0] on write for a single CSChris Packham2018-01-193-8/+13
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* armv8: ls1088a: Add NXP LS1088A SoC supportAshish Kumar2017-09-111-1/+1
* env: Rename getenv/_f() to env_get()Simon Glass2017-08-163-8/+8
* arm: mvebu: ddr3_debug: remove self assignmentsxypron.glpk@gmx.de2017-08-131-9/+0
* arm: mvebu: remove self assignmentxypron.glpk@gmx.de2017-08-131-2/+0
* driver/ddr: Add support for setting timing in hws_topology_mapMarek Behún2017-07-122-0/+15
* treewide: remove unneeded semicolonsMasahiro Yamada2017-06-161-1/+1
* driver: ddr: fsl: Fix compiling error for DDR2York Sun2017-06-121-0/+4
* common: arm: freescale: layerscape: Move header files out of common.hSimon Glass2017-06-054-4/+8
* common: freescale: Move arch-specific declarationsSimon Glass2017-06-055-0/+13
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-04-181-36/+36
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| * drivers: ddr: fsl: fix unused-const-variable warningsThomas Schaefer2017-04-171-36/+36
* | ddr: fsl: incorrect logical constraint in populate_memctl_optionsxypron.glpk@gmx.de2017-04-181-1/+1
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* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2017-04-143-1/+9
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| * arm: socfpga: Convert Altera DDR SDRAM driver to use KconfigLey Foon Tan2017-04-143-1/+9
* | board_f: Rename initdram() to dram_init()Simon Glass2017-04-131-2/+2
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