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* ddr: altera: Remove unnecessary update of the SCCMarek Vasut2016-04-201-1/+0
* ddr: altera: Fix DRAM end value in protection ruleMarek Vasut2016-04-201-1/+1
* ddr: altera: Fix scc_mgr_set() argument orderMarek Vasut2016-04-201-1/+1
* ddr: altera: Tweak DQS tracking enable handlingMarek Vasut2016-04-201-2/+5
* ddr: altera: Replace ad-hoc constant with macroMarek Vasut2016-04-201-2/+2
* Fix typo choosen in comments and printf logsAlexander Merkle2016-03-271-2/+2
* arm: mvebu: Fix ddr3_init() cpu configDirk Eibach2016-03-241-2/+0
* driver/ddr/fsl: Add workaround for erratum A-009803Shengzhou Liu2016-03-211-5/+39
* driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discreteShengzhou Liu2016-03-212-7/+63
* Use correct spelling of "U-Boot"Bin Meng2016-02-061-1/+1
* drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.Purna Chandra Mandal2016-02-014-0/+497
* drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllersEd Swarthout2016-01-251-0/+1
* driver/ddr/fsl: Add workaround for A009663Shengzhou Liu2016-01-251-0/+10
* fsl/ddr: Add workaround for ERRATUM_A009942Shengzhou Liu2016-01-251-0/+18
* Add more SPDX-License-Identifier tagsTom Rini2016-01-1910-30/+10
* ddr: altera: Init the rule ID in debug codeMarek Vasut2016-01-161-0/+1
* mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BITPhil Sutter2016-01-142-11/+11
* axp: Fix debugging support in DDR3 write levelingPhil Sutter2016-01-141-2/+2
* arm: mvebu: Make ECC support configurable on Armada XPStefan Roese2016-01-142-0/+8
* arm: mvebu: ddr: Fix compilation warningStefan Roese2016-01-142-17/+0
* move erratum a008336 and a008514 to soc specific fileYao Yuan2015-12-151-34/+0
* fsl/ddr: updated ddr errata-A008378 for arm and power SoCsShengzhou Liu2015-12-131-3/+6
* driver/ddr/fsl: Update timing config for heavy loadYork Sun2015-12-131-2/+24
* driver/ddr/fsl: Update workaround for A008511 for vref rangeYork Sun2015-12-131-7/+15
* driver/ddr/fsl: Update MR5 RTT parkYork Sun2015-12-131-4/+15
* driver/ddr/fsl: Update DDR4 MR6 for Vref rangeYork Sun2015-12-131-0/+3
* driver/ddr/fsl: Update DDR4 RTT valuesYork Sun2015-12-131-2/+235
* drivers/ddr/fsl: Fix typo in BIST test for DDR4York Sun2015-11-301-12/+12
* drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3York Sun2015-11-302-0/+41
* armv8: ls2085a: Add support of LS2085A SoCPrabhakar Kushwaha2015-11-301-2/+2
* armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha2015-11-301-2/+2
* arm: mvebu: Fix SAR1_CPU_CORE_MASKDirk Eibach2015-11-171-5/+2
* arm: mvebu: a38x: Remove unsupported topologiesKevin Smith2015-11-172-77/+0
* Various Makefiles: Add SPDX-License-Identifier tagsTom Rini2015-11-101-3/+1
* drivers/ddr/fsl_ddr: Make SR_IE configurableJoakim Tjernlund2015-10-301-1/+1
* bitops: introduce BIT() definitionHeiko Schocher2015-09-111-2/+0
* ddr: altera: Repair uninited variableMarek Vasut2015-08-231-1/+1
* ddr: altera: Replace float multiplication with integer oneMarek Vasut2015-08-231-1/+1
* arm: mvebu: Add complete SDRAM ECC scrubbingStefan Roese2015-08-172-2/+2
* arm: mvebu: sdram: Enable ECC support on Armada XPStefan Roese2015-08-171-1/+1
* ddr: altera: sequencer: Clean checkpatch issuesMarek Vasut2015-08-081-71/+88
* ddr: altera: sequencer: Clean data typesMarek Vasut2015-08-081-48/+48
* ddr: altera: sequencer: Pluck out misc macros from codeMarek Vasut2015-08-081-22/+15
* ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VALMarek Vasut2015-08-082-49/+4
* ddr: altera: sequencer: Zap VFIFO_SIZEMarek Vasut2015-08-082-7/+4
* ddr: altera: sequencer: Wrap misc remaining macrosMarek Vasut2015-08-081-0/+2
* ddr: altera: sequencer: Pluck out IO_* macros from codeMarek Vasut2015-08-081-101/+100
* ddr: altera: sequencer: Wrap IO_* macrosMarek Vasut2015-08-081-0/+2
* ddr: altera: sequencer: Pluck out RW_MGR_* macros from codeMarek Vasut2015-08-082-154/+154
* ddr: altera: sequencer: Wrap RW_MGR_* macrosMarek Vasut2015-08-081-0/+4
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