summaryrefslogtreecommitdiff
path: root/drivers/ddr
Commit message (Expand)AuthorAgeFilesLines
* Merge tag 'u-boot-imx-20200108' of https://gitlab.denx.de/u-boot/custodians/u...Tom Rini2020-01-081-0/+4
|\
| * ddr: imx8m: Add DRAM PLL to generate 1000Mhz outputPeng Fan2020-01-081-0/+4
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2020-01-088-458/+691
|\ \
| * | ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC AccessThor Thayer2020-01-072-6/+6
| * | arm: socfpga: stratix10: Enable SMMU accessThor Thayer2020-01-071-0/+14
| * | ddr: altera: agilex: Add SDRAM driver for AgilexLey Foon Tan2020-01-075-3/+174
| * | ddr: altera: Restructure Stratix 10 SDRAM driverLey Foon Tan2020-01-075-443/+493
| * | arm: socfpga: Move Stratix10 and Agilex system manager common codeLey Foon Tan2020-01-071-1/+1
| * | arm: socfpga: Move firewall code to firewall fileLey Foon Tan2020-01-071-1/+1
| * | arm: socfpga: Convert system manager from struct to definesLey Foon Tan2020-01-072-10/+8
* | | Merge tag 'u-boot-imx-20200107' of https://gitlab.denx.de/u-boot/custodians/u...WIP/07Jan2020Tom Rini2020-01-073-8/+20
|\ \ \ | |/ / |/| / | |/
| * ddr: imx8m: Return error values from LPDDR4 trainingFrieder Schrempf2020-01-073-8/+20
* | Merge branch 'next'WIP/06Jan2020Tom Rini2020-01-061-7/+6
|\ \ | |/ |/|
| * mpc85xx: ddr: Always start DDR RAM in Self Refresh modeJoakim Tjernlund2019-12-231-7/+6
* | imx8m: ddr_init: Move ddr_init() messages to debug levelFabio Estevam2019-12-271-3/+3
|/
* common: Move some cache and MMU functions out of common.hSimon Glass2019-12-022-0/+2
* ddr: socfpga: gen5: constify altera_gen5_sdram_opsSimon Goldschmidt2019-11-201-1/+1
* ddr: imx8m: Fix the ddr init hang on imx8mqJacky Bai2019-10-081-4/+4
* driver: ddr: Refine the ddr init driver on imx8mJacky Bai2019-10-087-311/+184
* imx8mq: Update the ddrc QoS setting for B1 chipBai Ping2019-10-081-1/+4
* ddr: imx8m: Fix ddr4 driver build issueYe Li2019-10-081-2/+1
* ddr: imx8m: fix ddr firmware location when enable SPL OFPeng Fan2019-10-081-1/+11
* ddr, fsl: add DM_I2C supportHeiko Schocher2019-08-261-43/+76
* boards: lx2160a: Add support of I2C driver modelChuanhua Han2019-08-221-1/+35
* env: Move env_get_f() to env.hSimon Glass2019-08-113-0/+3
* dm: ddr: socfpga: fix gen5 ddr driver to not use bssSimon Goldschmidt2019-07-212-642/+740
* mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASEMario Six2019-05-211-0/+4
* arm: socfpga: Move Stratix 10 SDRAM driver to DMLey Foon Tan2019-05-063-77/+360
* ddr: altera: Compile ALTERA SDRAM in SPL onlyLey Foon Tan2019-05-062-3/+4
* ddr: imx8m: hide i.MX8M DDR options from device driver entryPeng Fan2019-04-251-0/+4
* ddr: altera: Stratix10: Add ECC memory scrubbingLey Foon Tan2019-04-171-0/+81
* ddr: altera: Stratix10: Add multi-banks DRAM size checkLey Foon Tan2019-04-171-5/+41
* ddr: altera: stratix10: Move SDRAM size check to SDRAM driverLey Foon Tan2019-04-171-0/+15
* arm: socfpga: move gen5 SDR driver to DMSimon Goldschmidt2019-04-174-16/+173
* arm: mvebu: Add Marvell's integrated CPUsChris Packham2019-04-121-0/+4
* mv_ddr: ddr3: only use active chip-selects when tuning ODTChris Packham2019-03-191-1/+2
* mv_ddr: ddr3: fix tRAS timimg parameterChris Packham2019-03-191-4/+4
* ddr: socfpga: Clean up ddr_setup()Marek Vasut2019-03-091-28/+15
* ddr: socfpga: Clean up EMIF resetMarek Vasut2019-03-091-26/+7
* ddr: socfpga: Fix EMIF clear timeoutMarek Vasut2019-03-091-14/+11
* ddr: socfpga: Fix newline in debug print on A10Marek Vasut2019-03-091-1/+1
* ddr: socfpga: Fix IO in Arria10 DDR driverMarek Vasut2019-03-091-3/+3
* configs: fsl: move DDR specific defines to KconfigRajesh Bhagat2019-03-031-0/+12
* drivers/ddr/fsl: Update fsl_ddr_board_options as weak functionPriyanka Jain2019-02-191-3/+6
* drivers: ddr: introduce DDR driver for i.MX8MPeng Fan2019-01-0110-0/+1510
* Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2018-12-101-0/+1
|\
| * armv8: lx2160a: Add LX2160A SoC SupportPriyanka Jain2018-12-061-0/+1
* | ARM: mvebu: restore license information in mv_ddr_plat.{c,h}Chris Packham2018-12-092-0/+9
* | ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02Chris Packham2018-12-0831-1254/+1156
|/
* socfpga: stratix10: fix sdram_calculate_sizeDalon Westergreen2018-09-151-2/+2
View Lorry Controller Status