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* arm: mvebu: fix A38x breakage from commit bb872dd930ccJoel Johnson2020-01-261-1/+1
| | | | | | | | | This function parameter usage of load_addr was incorrectly caught in the clarifying renames of commit bb872dd930cc, which results in boot failures on Marvell A38x. Signed-off-by: Joel Johnson <mrjoel@lixil.net> Patch-to: Simon Glass <sjg@chromium.org>
* ddr: marvell: a38x: allow board specific clock out setupBaruch Siach2020-01-212-2/+11
| | | | | | | | | | DDR clock out might be unrelated to the number of active chip-select. For example, the board might have two DDR components, but only one chip-select. The clk_enable mask allows the board to enable DDR clocks regardless of active chip-selects. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
* common: Move hang() to the same header as panic()Simon Glass2020-01-173-0/+3
| | | | | | | | | | At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
* common: Move RAM-sizing functions to init.hSimon Glass2020-01-172-0/+2
| | | | | | | These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Move the image globals into image.hSimon Glass2020-01-171-0/+1
| | | | | | | These three globals relate to image handling. Move them to the image header file. Signed-off-by: Simon Glass <sjg@chromium.org>
* image: Rename load_addr, save_addr, save_sizeSimon Glass2020-01-171-3/+3
| | | | | | | | | These global variables are quite short and generic. In fact the same name is more often used locally for struct members and function arguments. Add a image_ prefix to make them easier to distinguish. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge tag 'u-boot-imx-20200108' of ↵Tom Rini2020-01-081-0/+4
|\ | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx --------------------------------------------------------------------- Add i.MX8MP SoC and EVK board Update README for i.MX8MN EVK and fix mmc env Add pca9450 driver -------------------------------------------------------------------- Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/634211885
| * ddr: imx8m: Add DRAM PLL to generate 1000Mhz outputPeng Fan2020-01-081-0/+4
| | | | | | | | | | | | | | We will generate DRAM 4000MT/s as default for i.MX8MP. So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2020-01-088-458/+691
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| * | ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC AccessThor Thayer2020-01-072-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ECC registers in the SDRAM HMC Adapter should always be accessible (both when ECC is enabled and disabled). Currently, the registers are accessible only when ECC is enabled. The ECC Enabled bit is used to determine the status of ECC by later OSes so always allow access. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | arm: socfpga: stratix10: Enable SMMU accessThor Thayer2020-01-071-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | Enable TCU access through the Stratix10 CCU so that the SMMU can access the SDRAM. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ddr: altera: agilex: Add SDRAM driver for AgilexLey Foon Tan2020-01-075-3/+174
| | | | | | | | | | | | | | | | | | | | | | | | Add SDRAM driver for Agilex SoC. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | ddr: altera: Restructure Stratix 10 SDRAM driverLey Foon Tan2020-01-075-443/+493
| | | | | | | | | | | | | | | | | | | | | | | | Restructure Stratix 10 SDRAM driver. Move common code to separate file, in preparation to support SDRAM driver for Agilex. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | arm: socfpga: Move Stratix10 and Agilex system manager common codeLey Foon Tan2020-01-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Move Stratix10 and Agilex system manager common code to system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | arm: socfpga: Move firewall code to firewall fileLey Foon Tan2020-01-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move firewall related code to new firewall.c, to share code in Stratix 10 and Agilex. SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC to allow DMA transfer to OCRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | arm: socfpga: Convert system manager from struct to definesLey Foon Tan2020-01-072-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* | | Merge tag 'u-boot-imx-20200107' of ↵WIP/07Jan2020Tom Rini2020-01-073-8/+20
|\ \ \ | |/ / |/| / | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx New for 2020.04 --------------- - New boards Embedded Artists COM board Xea Board - Switch to DM: Aristainetos boards Toradex colibri (DM_ETH) iCubox GE bx50v3 mx7dsabre (DM_ETH) cx9020 - New features: Bootaux with elf files Default SYS_THUMB_BUILD for i.MX6/7 - Fixes: DHCOM i.MX6 PDK Engicam i.MX8M tools (imx8m_image) Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
| * ddr: imx8m: Return error values from LPDDR4 trainingFrieder Schrempf2020-01-073-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | In cases when the same SPL should run on boards with i.MX8MM, that differ in DDR configuration, it is necessary to try different parameters and check if the training done by the firmware suceeds or not. Therefore we return the DDR training/initialization success to the upper layer in order to be able to retry with different settings if necessary. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
* | Merge branch 'next'WIP/06Jan2020Tom Rini2020-01-061-7/+6
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bring in the following merges: commit 8fbbec12f7d2c18f8883f3371cfca74a98b5dd87 Merge: 87f69f467a83 63618e71e89b Author: Tom Rini <trini@konsulko.com> Date: Fri Jan 3 09:48:47 2020 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next - updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support commit 87f69f467a8335b171c71bf217d2625d515acd7c Merge: c0912f9bbfb2 4466b9970319 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 24 08:18:19 2019 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next - Enable DM driver on ppc/km boards - Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x, T104x, P4080, P2041, P2020, P1020, P3041 - Some updates in mpc85xx-ddr driver, km boards commit c0912f9bbfb26dd03d189953678691b799d35b6e Merge: 533c9f5714bd a1d6dc3f8407 Author: Tom Rini <trini@konsulko.com> Date: Wed Dec 18 07:20:19 2019 -0500 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next - Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral commit 533c9f5714bdba79dc6f2629284d4c1a08a611d1 Merge: 553cb0688782 033e18b47bd0 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 17 07:53:08 2019 -0500 Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next i2c: for next - misc: i2c_eeprom: Add partition support and add ability to query size of eeprom device and partitions - i2c common: add support for offset overflow in to address and add sandbox tests for it. commit 553cb06887825314e74a9bdac337467c77d1db88 Merge: f39abbbc531e b4f98b3b16ec Author: Tom Rini <trini@konsulko.com> Date: Thu Dec 12 08:18:59 2019 -0500 Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next buildman improvements including toolchain environment feature sandbox unicode support in serial
| * mpc85xx: ddr: Always start DDR RAM in Self Refresh modeJoakim Tjernlund2019-12-231-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | Some of t1042 boards fails DDR init with an Automatic calibration error every now and then. Investigations revealed that true Warm boots never failed. Warm boots has some extra steps performed, one being to start DDRC in Self Refresh and then clearing SR right after. Applying this SR method unconditionally made all our boards stable again, regardless of Cold/Warm boot. Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* | imx8m: ddr_init: Move ddr_init() messages to debug levelFabio Estevam2019-12-271-3/+3
|/ | | | | | | | | | | Currently inside ddr_init() there is a mix of printf() and debug() level messages. Since this type of information is useful for debug purposes, convert all of them to debug level for consistency. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* common: Move some cache and MMU functions out of common.hSimon Glass2019-12-022-0/+2
| | | | | | | | | | | | These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ddr: socfpga: gen5: constify altera_gen5_sdram_opsSimon Goldschmidt2019-11-201-1/+1
| | | | | | | | | Make the function pointer struct const, as it does not need to be writable. This doesn't really change anything other than moving this variable to a different section. No functional change. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* ddr: imx8m: Fix the ddr init hang on imx8mqJacky Bai2019-10-081-4/+4
| | | | | | | | | | On, i.MX8MQ, the PLL config must be done when ddrmix isolation is released. So move the dram pll init after iso config done. For other i.MX8M SOC, either init pll before or after isolation is ok. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* driver: ddr: Refine the ddr init driver on imx8mJacky Bai2019-10-087-311/+184
| | | | | | | | | | Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mq: Update the ddrc QoS setting for B1 chipBai Ping2019-10-081-1/+4
| | | | | | | | | | | | Update the ddrc Qos setting for B1 to align with B0's setting. Correct the initial clock for dram_pll. This setting will be overwrite before ddr phy training. Although there is no impact on the dram init, we still need to correct it to eliminate confusion. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Tested-by: Robby Cai <robby.cai@nxp.com>
* ddr: imx8m: Fix ddr4 driver build issueYe Li2019-10-081-2/+1
| | | | | | | | Since the parameter of dram_pll_init is changed, update to use new. Also remove non-existed header file. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* ddr: imx8m: fix ddr firmware location when enable SPL OFPeng Fan2019-10-081-1/+11
| | | | | | | | | | | With CONFIG_SPL_OF_CONTROL, the device tree will be padded to end of the u-boot-spl-nodtb.bin, however we also put the ddr firmware file to this location, so need to adapt the code with SPL OF and align to 4 bytes to ease copy firmware. Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* ddr, fsl: add DM_I2C supportHeiko Schocher2019-08-261-43/+76
| | | | | | | add DM_I2C support for this driver. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* boards: lx2160a: Add support of I2C driver modelChuanhua Han2019-08-221-1/+35
| | | | | | | | | | | DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C API when DM_I2C is used. When DM_I2C_COMPAT is not enabled for compilation, a compilation error will be generated. This patch solves the problem that the i2c-related api of the lx2160a platform does not support dm. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* env: Move env_get_f() to env.hSimon Glass2019-08-113-0/+3
| | | | | | | Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* dm: ddr: socfpga: fix gen5 ddr driver to not use bssSimon Goldschmidt2019-07-212-642/+740
| | | | | | | | | | This driver uses bss from SPL board_init_f(). Change it to move all the data from bss to a common struct allocated on the stack (64 byte). In addition to saving 28 bytes of bss, the code even gets 264 bytes smaller. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASEMario Six2019-05-211-0/+4
| | | | | | | | CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as CONFIG_SYS_SDRAM_BASE on all existing boards. Just use CONFIG_SYS_SDRAM_BASE instead. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* arm: socfpga: Move Stratix 10 SDRAM driver to DMLey Foon Tan2019-05-063-77/+360
| | | | | | | | | | | | | | Convert Stratix 10 SDRAM driver to device model. Get rid of call to socfpga_per_reset() and use reset framework. SPL is changed from calling function in SDRAM driver directly to just probing UCLASS_RAM. Move sdram_s10.h from arch to driver/ddr/altera directory. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* ddr: altera: Compile ALTERA SDRAM in SPL onlyLey Foon Tan2019-05-062-3/+4
| | | | | | | Compile ALTERA_SDRAM driver in SPL only. Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* ddr: imx8m: hide i.MX8M DDR options from device driver entryPeng Fan2019-04-251-0/+4
| | | | | | | Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* ddr: altera: Stratix10: Add ECC memory scrubbingLey Foon Tan2019-04-171-0/+81
| | | | | | | | | | | | | Scrub memory content if ECC is enabled and it is not from warm reset boot. Enable icache and dcache before scrub memory and use "DC ZVA" instruction to clear memory to zeros. This instruction writes a cache line at a time and it can prevent false ECC error trigger if write cache line partially. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* ddr: altera: Stratix10: Add multi-banks DRAM size checkLey Foon Tan2019-04-171-5/+41
| | | | | | | | | | | Stratix 10 maps dram from 0 to 128GB. There is a 2GB hole in the memory for peripherals and other IO from 2GB to 4GB. However the dram controller ignores upper address bits for smaller dram configurations. Example: a 4GB dram maps to multiple locations, every 4GB on the address. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* ddr: altera: stratix10: Move SDRAM size check to SDRAM driverLey Foon Tan2019-04-171-0/+15
| | | | | | | | Move SDRAM size check to SDRAM driver. sdram_calculate_size() is called in SDRAM initialization already, avoid calling twice in size check function. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: move gen5 SDR driver to DMSimon Goldschmidt2019-04-174-16/+173
| | | | | | | | | | | | | | | | | To clean up reset handling for socfpga gen5, port the DDR driver to DM using UCLASS_RAM and implement proper reset handling. This gets us rid of one ad-hoc call to socfpga_per_reset(). The gen5 driver is implemented in 2 distinct files. One of it (containing the calibration training) is not touched much and is kept at using hard coded addresses since the code grows even more otherwise. SPL is changed from calling hard into the DDR driver code to just probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM driver after that. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: mvebu: Add Marvell's integrated CPUsChris Packham2019-04-121-0/+4
| | | | | | | | | | | | Marvell's switch chips with integrated CPUs (collectively referred to as MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks (e.g. xor) are located at different addresses and DFX server exists as a separate target on the MBUS (on Armada-38x it's just part of the core complex registers). Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* mv_ddr: ddr3: only use active chip-selects when tuning ODTChris Packham2019-03-191-1/+2
| | | | | | | | | | | Inactive chip-selects will give invalid values for read_sample so don't consider them when trying to determine the overall min/max read sample. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> [https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/18] Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mv_ddr: ddr3: fix tRAS timimg parameterChris Packham2019-03-191-4/+4
| | | | | | | | | | | | | Based on the JEDEC standard JESD79-3F. The tRAS timings should include the highest speed bins at a given frequency. This is similar to commit 683c67b ("mv_ddr: ddr3: fix tfaw timimg parameter") where the wrong comparison was used in the initial implementation. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> [https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/15] Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ddr: socfpga: Clean up ddr_setup()Marek Vasut2019-03-091-28/+15
| | | | | | | | | | | | | | | | Replace the current rather convoluted code using ad-hoc polling mechanism with a more straightforward code. Use wait_for_bit_le32() to poll the DDRCALSTAT register instead of local reimplementation. It makes no sense to pull for 5 seconds before giving up and trying to restart the EMIF, so instead wait 500 mSec for the calibration to complete and if this fails, restart the EMIF and try again. Perform this 32 times instead of 3 times as the original code did. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* ddr: socfpga: Clean up EMIF resetMarek Vasut2019-03-091-26/+7
| | | | | | | | | | | | | | The EMIF reset code can well use wait_for_bit_le32() instead of all that convoluted polling code. Reduce the timeout from 100 seconds to 1 second, since if the EMIF fails to reset itself in 1 second, it's unlikely longer wait would help. Make sure to clear the EMIF reset request even if the SEQ2CORE_INT_RESP_BIT isn't asserted. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* ddr: socfpga: Fix EMIF clear timeoutMarek Vasut2019-03-091-14/+11
| | | | | | | | | | | | | | | | The current EMIF clear timeout handling code was applying bitwise operations to signed data types and as it was, was extremely hard to read. Replace it with simple wait_for_bit(). Expand the error handling to make it more readable too. This patch also changes the timeout for emif_clear() from 14 hours to 1 second. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* ddr: socfpga: Fix newline in debug print on A10Marek Vasut2019-03-091-1/+1
| | | | | | | | | | The debug print is missing a newline, add it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* ddr: socfpga: Fix IO in Arria10 DDR driverMarek Vasut2019-03-091-3/+3
| | | | | | | | | | | | The Altera Arria10 DDR driver was using constants in a few places instead of reading registers associated with those constants, fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* configs: fsl: move DDR specific defines to KconfigRajesh Bhagat2019-03-031-0/+12
| | | | | | | | | | | | | Moves below DDR specific defines to Kconfig: CONFIG_FSL_DDR_BIST CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE CONFIG_FSL_DDR_INTERACTIVE CONFIG_FSL_DDR_SYNC_REFRESH Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* drivers/ddr/fsl: Update fsl_ddr_board_options as weak functionPriyanka Jain2019-02-191-3/+6
| | | | | | | | | | | | fsl_ddr_board_options is generally defined in board board's ddr.c, but some boards like lx2160ardb board does not need this function. Defining fsl_ddr_board_options as weak function to resolve compilation errors for such boards. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> [PK: Fix checkpatch warnings] Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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