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path: root/drivers/ddr/marvell
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* ddr: marvell: update ddr controller init and freqChris Packham2018-01-193-21/+34
* ddr: marvell: update additional ODT settingChris Packham2018-01-191-8/+14
* ddr: marvell: use correct TREFI valueChris Packham2018-01-191-1/+1
* ddr: marvell: only assert M_ODT[0] on write for a single CSChris Packham2018-01-193-8/+13
* arm: mvebu: ddr3_debug: remove self assignmentsxypron.glpk@gmx.de2017-08-131-9/+0
* arm: mvebu: remove self assignmentxypron.glpk@gmx.de2017-08-131-2/+0
* driver/ddr: Add support for setting timing in hws_topology_mapMarek Behún2017-07-122-0/+15
* treewide: remove unneeded semicolonsMasahiro Yamada2017-06-161-1/+1
* Various, accumulated typos collected from around the tree.Robert P. J. Day2016-10-061-1/+1
* drivers: squash lines for immediate returnMasahiro Yamada2016-09-231-5/+1
* arm: mvebu: a38x: Weed out floating point useMarek Vasut2016-05-201-19/+10
* Fix spelling of "occurred".Vagrant Cascadian2016-05-022-2/+2
* arm: mvebu: Fix ddr3_init() cpu configDirk Eibach2016-03-241-2/+0
* Use correct spelling of "U-Boot"Bin Meng2016-02-061-1/+1
* mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BITPhil Sutter2016-01-142-11/+11
* axp: Fix debugging support in DDR3 write levelingPhil Sutter2016-01-141-2/+2
* arm: mvebu: Make ECC support configurable on Armada XPStefan Roese2016-01-142-0/+8
* arm: mvebu: ddr: Fix compilation warningStefan Roese2016-01-142-17/+0
* arm: mvebu: Fix SAR1_CPU_CORE_MASKDirk Eibach2015-11-171-5/+2
* arm: mvebu: a38x: Remove unsupported topologiesKevin Smith2015-11-172-77/+0
* bitops: introduce BIT() definitionHeiko Schocher2015-09-111-2/+0
* arm: mvebu: Add complete SDRAM ECC scrubbingStefan Roese2015-08-172-2/+2
* arm: mvebu: sdram: Enable ECC support on Armada XPStefan Roese2015-08-171-1/+1
* arm: mvebu: a38x: Use correct PEX register access macrosStefan Roese2015-07-231-5/+0
* arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdrStefan Roese2015-07-2343-0/+17368
* arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directoryStefan Roese2015-07-2321-0/+15419
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