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* common: Drop linux/delay.h from common headerSimon Glass2020-05-1818-0/+18
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/stringify.h from common headerSimon Glass2020-05-186-0/+6
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/bug.h from common headerSimon Glass2020-05-185-0/+5
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop asm/ptrace.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop log.h from common headerSimon Glass2020-05-1851-0/+51
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* command: Remove the cmd_tbl_t typedefSimon Glass2020-05-181-1/+3
| | | | | | | | | | | | | We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop init.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop net.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | | | | | | Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge tag 'u-boot-stm32-20200514' of ↵WIP/14May2020Tom Rini2020-05-141-3/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-stm - stm32mp1: migrate MTD and DFU configuration in Kconfig - stm32mp1: add command stm32prog - stm32mp1: several board and arch updates - stm32mp1: activate data cache in SPL and before relocation - Many improvment for AV96 board and DHCOR SoM (add new defconfig, DDR3 coding on DHCOR SoM, split between board and SOM Synchronize DDR setttings on DH SoMs, setting for I2C EEPROM) - clk: stm32mp1: fix CK_MPU calculation - DT alignment of stm32mp1 device tree with Linux 5.7-rc2
| * clk: stm32mp1: fix CK_MPU calculationLionel Debieve2020-05-141-3/+4
| | | | | | | | | | | | | | | | | | When the CK_MPU used PLL1_MPUDIV, the current rate is wrong. The clock must use stm32mp1_mpu_div as a shift value. Fix the check value used to enter PLL_MPUDIV. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | CLK: ARC: HSDK: add separate clock map for HSDK-4xDEugeniy Paltsev2020-05-132-11/+64
| | | | | | | | | | | | | | | | | | | | | | HSDK and HSDK-4xD clock trees are slightly different. commit 1dfb2ec0d7fb ("ARC: HSDK: CGU: add support for timer clock") introduce regression for HSDK board cause crash when setting tunnel clock. Fix that. Fixes: 1dfb2ec0d7fb ("ARC: HSDK: CGU: add support for timer clock") Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | CLK: ARC: HSDK: define clock map with DT binding constantsEugeniy Paltsev2020-05-131-27/+29
| | | | | | | | | | | | | | | | Define clock map with DT binding constants so clock map can be discontinuous. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | CLK: ARC: HSDK: make set_clock optionalEugeniy Paltsev2020-05-131-1/+4
| | | | | | | | | | | | | | | | We don't want to allow change some clocks, i.e. DDR clock. So allow to have set_clock to be unset in clock map. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | CLK: ARC: HSDK: prepare for multiple clock maps supportEugeniy Paltsev2020-05-131-7/+20
| | | | | | | | | | | | | | | | The clock trees of HSDK and HSDK-4xD vary so we need to prepare CGU driver for multiple clock maps support. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | CLK: ARC: HSDK: driver cleanupEugeniy Paltsev2020-05-131-36/+39
| | | | | | | | | | | | | | Minor code cleanup to improve readability. No functional change intended. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | CLK: ARC: HSDK: use appropriate config data typesEugeniy Paltsev2020-05-131-20/+21
| | | | | | | | | | | | | | | | * constify clocks config data where is possible * use more appropriate data types for clocks config Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | CLK: ARC: HSDK: drop unused offsetEugeniy Paltsev2020-05-131-29/+28
| | | | | | | | | | | | | | | | Drop creg_div_oft offset as it doesn't vary (due to it is used for CPU PLL only). Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | CLK: ARC: HSDK: avoid code duplicationEugeniy Paltsev2020-05-131-72/+40
|/ | | | | | | | | hsdk_axi_clk_cfg and hsdk_tun_clk_cfg clock divider structures and functions for their processing are almost the same so merge them to avoid code duplication. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* Merge tag 'u-boot-imx-20200502' of ↵Tom Rini2020-05-041-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX for 2020.07 ---------------- - imxrt: fix LCD clock, fix doc - new board: Coral Dev - imx8: enable Cache in SPL. SNVS, update SCFW API - imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading - MX6ULL : is_imx6ull to include i.MX6ULZ - Net: add config to enable TXC delay Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914
| * clk: imx: clk-imxrt1050: fix lcdif clock gateGiulio Benetti2020-05-011-1/+1
| | | | | | | | | | | | | | | | LCDIF clock gate was wrong so set it according to RM. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* | Merge tag 'u-boot-rockchip-20200501' of ↵Tom Rini2020-05-041-0/+1
|\ \ | |/ |/| | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - dts clean up to use -u-boot for px30, rk3399 boards - dts sycn from upstream kernel for rk3328, rk3399 - add rockchip rng driver - new board support: rk3328-roc-cc, rk3399-roc-pc,Nanopi M4 2GB
| * clk: rk3399: Set empty for HCLK_SD assigned-clocksJagan Teki2020-05-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi have HCLK_SD assigned-clocks which are usually required for Linux and don't require to handle them in U-Boot. assigned-clocks = <&cru HCLK_SD>; So, mark them as empty in clock otherwise device probe on those SD controllers would fail. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | Merge tag 'xilinx-for-v2020.07-rc2' of ↵Tom Rini2020-04-301-1/+4
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2020.07-rc2 mmc: - Fix dt property handling via generic function clk: - Fix versal watchdog clock setting nand: - Fix zynq nand command comparison xilinx: - Enable ubifs - Sync board_late_init configurations with initrd_high setup - Make custom distro boot more verbose zynq: - Kconfig alignments - Fix nand cse configuration zynqmp: - Fix zcu104 low level qspi configuration - Small DT updates Signed-off-by: Tom Rini <trini@konsulko.com>
| * | clk: versal: Fix watchdog clock issueT Karthik Reddy2020-04-271-1/+4
| |/ | | | | | | | | | | | | | | | | Enable mux based clocks to populate LPD_LSBUS clock to xilinx_wwdt driver. Skip reading clock rate for the mux based clocks with parent clock id is zero. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
* | Merge tag 'u-boot-amlogic-20200428' of ↵Tom Rini2020-04-281-0/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - fix sd-emmc controller A init on G12A/G12B/SM1 SoCs - add GXBB USB PHY driver - enable access to SPI NOR Flash on VIM2 and VIM3/VIM3L boards - fix USB PHYs Power-Up on on VIM3/VIM3L boards
| * | clk: meson: g12a: add missing SD_EMMC_A controller gatesNeil Armstrong2020-04-281-0/+2
| |/ | | | | | | | | | | | | | | Add missing SD_EMMC_A controller gates needed for probe of the A controller, otherwise leading to a freeze of the SoC after b3d69aa596. Fixes: b3d69aa596 ("clk: meson: reset mmc clock on probe") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | ARC: HSDK: CGU: add support for timer clockEugeniy Paltsev2020-04-271-3/+6
|/ | | | | | | | Add support for additional timer clock which belongs to tunnel domain. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* clk: actions: Add common clock driverAmit Singh Tomar2020-04-244-34/+112
| | | | | | | | This patch converts S900 clock driver to something common that can be used for other SoCs, for instance S700(few of clk registers are same). Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
* arm: dts: sync dts for Action Semi S900Amit Singh Tomar2020-04-241-3/+3
| | | | | | | | | | | | | Synchronize device tree bindings with v5.5-rc6 tag with commit id "b3a987b0264d". Also, it removes older clock binding defined for S900 along with undocumented compatible string "actions,s900-serial" from serial driver and adapts clock driver to cater to new bindings. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
* clk: armada-37xx-periph: fix DDR PHY clock divider valuesMarek Behún2020-04-221-2/+2
| | | | | | | | | | | | Register value table for DDR PHY clock divider are wrong. They should be 0 or 1 for divide-by-2 or divide-by-4, respectively. Not 1 or 2. Current values do not make sense, since 2 cannot be achieved, because the register is only 1 bit long (mask is set to 1). This fixes clk dump reporting DDR PHY clock rate differently from Linux. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* clk: imx: add i.IMXRT1020 clk driverGiulio Benetti2020-04-183-0/+244
| | | | | | | Add i.MXRT1020 clk driver support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: clk-imxrt1050: add set_parent() callbackGiulio Benetti2020-04-181-0/+19
| | | | | | | Need to add set_parent() callback to allow dts assigned-clock-parents to work so let's add it accordingly. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* clk: imx: clk-imxrt1050: setup PLL5 for video in non-SPLGiulio Benetti2020-04-181-1/+8
| | | | | | | | mxsfb needs PLL5 as source, so let's setup it at its default frequency specified in RM(650Mhz). Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: clk-imxrt1050: fix typo in clock name "video:"Giulio Benetti2020-04-181-1/+1
| | | | | | | "video:" must be "video", ":" is a typo. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: pllv3: add enable_bitGiulio Benetti2020-04-181-0/+9
| | | | | | | | | pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* Merge tag 'arc-fixes-for-2020.07-rc1' of ↵Tom Rini2020-04-161-1/+2
|\ | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-arc This is pretty minor set of changes mostly touching HSDK board: * Enable on-chip reset controller on HSDK * Add possibility to turn-on & off L2$ on more recent ARC HS processors. * AXI tunnel clock calculation on HSDK
| * ARC: HSDK: CGU: fix tunnel clock calculationEugeniy Paltsev2020-04-161-1/+2
| | | | | | | | | | | | | | | | We set wrong tunnel PLL frequency when we request 125MHz tunnel clock. Fix that. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | dm: core: remove the duplicated function dm_ofnode_pre_relocPatrick Delaunay2020-04-162-2/+2
|/ | | | | | | | | | | | | | The content dm_ofnode_pre_reloc() is identical with ofnode_pre_reloc() defined in drivers/core/ofnode.c and used only three times: - drivers/core/lists.c:lists_bind_fdt() - drivers/clk/at91/pmc.c::at91_clk_sub_device_bind - drivers/clk/altera/clk-arria10.c::socfpga_a10_clk_bind So this function dm_ofnode_pre_reloc can be removed and replaced by these function calls by ofnode_pre_reloc(). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Simon Glass <sjg@chromium.org>
* configs: stm32mp1: replace STM32MP1_TRUSTED by TFABOOTPatrick Delaunay2020-04-151-1/+1
| | | | | | | | | | | | Activate ARCH_SUPPORT_TFABOOT and replace the arch stm32mp specific config CONFIG_STM32MP1_TRUSTED by the generic CONFIG_TFABOOT introduced by the commit 535d76a12150 ("armv8: layerscape: Add TFABOOT support"). This config CONFIG_TFABOOT is activated for the trusted boot chain, when U-Boot is loaded by TF-A. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* Merge branch 'next'Tom Rini2020-04-134-3/+32
|\ | | | | | | | | | | | | | | | | | | | | Pull in changes that have been pending in our 'next' branch. This includes: - A large number of CI improvements including moving to gcc-9.2 for all platforms. - amlogic, xilinx, stm32, TI SoC updates - USB and i2c subsystem updtaes - Re-sync Kbuild/etc logic with v4.19 of the Linux kernel. - RSA key handling improvements
| * Merge tag 'u-boot-amlogic-20200406' of ↵WIP/08Apr2020-nextTom Rini2020-04-083-0/+22
| |\ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic into next - clk: meson-g12a: missing break - sync all Amlogic DT from Linux v5.6-rc2 - MMC clock fixups - add support for Libre Computer AML-S905D-PC and AML-S912-PC
| | * clk: meson: reset mmc clock on probeJerome Brunet2020-04-063-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some SoCs, depending on the boot device, the MMC clock block may be left in a weird state by the ROM code, in which no decent clock may be provided. Reset the related register to make sure a sane MMC clock is ready for the controller. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| | * clk: meson-g12a: missing breakHeinrich Schuchardt2020-04-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing break for CLKID_PCIE_PLL in switch statement. Reported by CppCheck. Cc: Neil Armstrong <narmstrong@baylibre.com> Fixes: 08e09c263fdf ("clk: meson-g12a: Add PCIE PLL support") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Lukasz Majewski <lukma@denx.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | Merge tag 'xilinx-for-v2020.07' of ↵WIP/07Apr2020-nextTom Rini2020-04-072-1/+9
| |\ \ | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2020.07 common: - Align ENV_FAT_INTERFACE - Fix MAC address source print log - Improve based autodetection code xilinx: - Enable netconsole Microblaze: - Setup default ENV_OFFSET/ENV_SECT_SIZE Zynq: - Multiple DT updates/fixes - Use DEVICE_TREE environment variable for DTB selection - Switch to single zynq configuration - Enable NOR flash via DM - Minor SPL print removal - Enable i2c mux driver ZynqMP: - Print multiboot register - Enable cache commands in mini mtest - Multiple DT updates/fixes - Fix firmware probing when driver is not enabled - Specify 3rd backup RAM boot mode in SPL - Add SPL support for zcu102 v1.1 and zcu111 revA - Redesign debug uart enabling and psu_init delay - Enable full u-boot run from EL3 - Enable u-boot.itb generation without ATF with U-Boot in EL3 Versal: - Enable distro default - Enable others SPI flashes - Enable systems without DDR Drivers: - Gem: - Flush memory after freeing - Handle mdio bus separately - Watchdog: - Get rid of unused global data pointer - Enable window watchdog timer - Serial: - Change reinitialization logic in zynq serial driver Signed-off-by: Tom Rini <trini@konsulko.com>
| * | clk: stm32mp1: add SPI5_K supportPatrick Delaunay2020-03-241-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Add clock support for SPI5, as this instance is available on extension connector of ST board. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
| * | clk: stm32mp1: correct CKSELR masksPatrick Delaunay2020-03-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Correct three masks used to access on the RCC register RCC_QSPICKSELR, RCC_FMCCKSELR and RCC_ADCCKSELR: only 3 bits. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
* | | clk: socfpga: Read the clock parent's register base in probe functionWIP/05Apr2020Chee Hong Ang2020-04-051-22/+18
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | This commit (82de42fa14682d408da935adfb0f935354c5008f) calls child's ofdata_to_platdata() method before the parent is probed in dm core. This has caused the driver no longer able to get the correct parent clock's register base in the ofdata_to_platdata() method because the parent clocks will only be probed after the child's ofdata_to_platdata(). To resolve this, the clock parent's register base will only be retrieved by the child in probe() method instead of ofdata_to_platdata(). Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | clk: rk3399: Set empty for vopl assigned-clocksJagan Teki2020-04-021-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During vidconsole probe, the device probe will try to check whether the assigned clocks on that video console node is initialized or not? and return an error if not. But, unlike Linux U-Boot won't require to handle these vopl assigned-clocks since core clocks are enough to handle the video out to process. So, mark them as empty in set_rate to satisfy clk_set_defaults so-that probe happened properly. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
* | clk: renesas: Switch to fdtdec_get_addr_size_auto_noparent() on Gen2Marek Vasut2020-03-301-1/+2
|/ | | | | | | | | | | | The fdtdec_get_addr() does not take into account values set in #address-cells and #size-cells , but assumes them to be 1 for 32bit systems and 2 for 64bit systems. This is true for most DTs, however there are exceptions. Switch to fdtdec_get_addr_size_auto_noparent(), which takes the #address/size-cells values into consideration, otherwise the reset controller node register offset is incorrectly parsed. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* x86: remove dead code in intel_clk_get_rate()Heinrich Schuchardt2020-03-051-4/+0
| | | | | | | | | | | If all branches of a switch statement have a return instruction, all subsequent lines are unreachable. Identified with cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
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