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* rockchip: rv1108: add ofdata_to_platdata() method for driverKever Yang2018-04-251-1/+9
* rockchip: rk3128: add ofdata_to_platdata() method for driverKever Yang2018-04-251-1/+10
* rockchip: rk3036: add ofdata_to_platdata() method for driverKever Yang2018-04-251-1/+10
* rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSICWadim Egorov2018-04-251-0/+13
* clk: uniphier: disable SPL_CLKMasahiro Yamada2018-04-241-1/+0
* clk: renesas: Minor clean up of the R8A7794 clock driverMarek Vasut2018-04-211-7/+3
* clk: renesas: Minor clean up of the R8A7792 clock driverMarek Vasut2018-04-211-7/+3
* Merge git://git.denx.de/u-boot-uniphierTom Rini2018-04-181-0/+6
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| * clk: uniphier: add ethernet clock control supportKunihiko Hayashi2018-04-181-0/+6
* | clk: fix clk_get_bulk when phandle errorNeil Armstrong2018-04-171-2/+2
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* clk: renesas: Minor clean up of the R8A7790 clock driverMarek Vasut2018-04-131-7/+3
* clk: add sandbox test for bulk APINeil Armstrong2018-04-101-0/+29
* clk: Add get/enable/disable/release for a bulk of clocksNeil Armstrong2018-04-101-0/+59
* clk: zynqmp: Add new compatible string for clock driverMichal Simek2018-04-091-0/+1
* clock: stm32mp1: add stgen clock source change supportPatrick Delaunay2018-04-061-1/+45
* rockchip: clk: rk3188: update dpll settings to make EMAC workAlexander Kochetkov2018-03-281-1/+1
* arm64: zynqmp: Print the value of pl clocks and wdt clock using clk dumpVipul Kumar2018-03-231-0/+75
* clk: zynq: Show watchdog clock rate properlyMichal Simek2018-03-231-1/+1
* clk: stm32mp1: add clock tree initializationPatrick Delaunay2018-03-191-0/+576
* clk: add driver for stm32mp1Patrick Delaunay2018-03-193-0/+1166
* clk: at91: clk-system: add set/get_rate operationsWenyou Yang2018-03-161-0/+26
* clk: at91: add PLLADIV driverWenyou Yang2018-03-162-1/+89
* clk: at91: add USB Host clock driverWenyou Yang2018-03-163-0/+155
* clk: clk_stm32f: Add DSI clock supportPatrice Chotard2018-03-131-1/+1
* clk: clk_stm32f: Add set_rate for LTDC clockPatrice Chotard2018-03-131-0/+100
* clk: clk_stm32f: Configure SAI PLL to generate LTDC pixel clockPatrice Chotard2018-03-131-1/+36
* clk: clk_stm32f: Rework SDMMC stm32_clk_get_rate() partPatrice Chotard2018-03-131-31/+74
* clk: clk_stm32f: No more need of 48Mhz from PLL_SAIPatrice Chotard2018-03-131-21/+8
* clk: clk_stm32f: Fix RCC_PLLSAICFGR mask definesPatrice Chotard2018-03-131-4/+4
* clk: clk_stm32f: Fix stm32_clk_get_rate()Patrice Chotard2018-03-131-5/+7
* board: stm32: switch to DM STM32 timerPatrice Chotard2018-03-131-15/+0
* clk: clk_stm32h7: Fix prescaler for Domain 3Patrice Chotard2018-03-131-3/+4
* clk: clk_stm32h7: Fix stm32_clk_get_rate() for timerPatrice Chotard2018-03-131-12/+90
* clk: clk_stm32f: Fix stm32_clk_get_rate() for timerPatrice Chotard2018-03-131-17/+99
* rockchip: clk: rk1108: convert to use live dtKever Yang2018-03-131-1/+1
* rockchip: clk: rk3328: convert to use live dtKever Yang2018-03-131-1/+1
* rockchip: clk: rk3288: convert to use live dtKever Yang2018-03-131-1/+1
* rockchip: clk: rk322x: convert to use live dtKever Yang2018-03-131-1/+1
* rockchip: clk: rk3188: convert to use live dtKever Yang2018-03-131-1/+1
* rockchip: clk: rk3036: convert to use live dtKever Yang2018-03-131-1/+1
* clk: renesas: Add R8A77965 M3N entriesMarek Vasut2018-03-051-0/+19
* rockchip: clk: rk3399: handle set_rate/get_rate for PLL_PPLLPhilipp Tomsich2018-02-241-0/+9
* rockchip: clk: rk3368: handle clk_enable requests for GMACPhilipp Tomsich2018-02-241-0/+19
* rockchip: clk: rk3399: handle clk_enable requests for GMACPhilipp Tomsich2018-02-241-0/+10
* clk: rmobile: Assure SD-IF clock are configured correctlyMarek Vasut2018-02-161-0/+2
* clk: clk_stm32: Add .set_rate callbackPatrice Chotard2018-01-291-0/+6
* Merge git://git.denx.de/u-boot-rockchipTom Rini2018-01-286-19/+701
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| * rockchip: clk: guard set_parent implementations against OF_PLATDATAPhilipp Tomsich2018-01-283-6/+12
| * clk: rockchip: clk_rk3368: Implement "assign-clock-parent"David Wu2018-01-281-7/+84
| * clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and "assign-clock-...David Wu2018-01-281-8/+98
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