summaryrefslogtreecommitdiff
path: root/drivers/clk
Commit message (Expand)AuthorAgeFilesLines
...
* | clk: at91: clk-generated: select absolute closest rateLudovic Desroches2017-11-291-3/+1
* | clk: at91: Kconfig: fix the dependency of AT91_UTMIWenyou Yang2017-11-291-3/+3
* | clk: clk_stm32fx: add clock configuration for mmc usagePatrice Chotard2017-11-291-1/+100
* | dm: misc: bind STM32F4/F7 clock from rcc MFD driverPatrice Chotard2017-11-291-41/+13
* | clk: stm32fx: migrate define from rcc.h to driverPatrice Chotard2017-11-291-1/+18
* | clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.cPatrice Chotard2017-11-293-9/+13
* | clk: stm32f7: add STM32F4 supportPatrice Chotard2017-11-291-43/+66
* | clk: stm32f7: add dedicated STM32F7 compatible stringPatrice Chotard2017-11-291-0/+1
* | clk: stm32f7: retrieve PWR base address from DTPatrice Chotard2017-11-291-11/+21
|/
* rockchip: clk: rk3399: change extract_bits to bitfield_extractPhilipp Tomsich2017-11-261-6/+2
* rockchip: clock: update sysreset driver bindingKever Yang2017-11-218-24/+112
* clk: clk_stm32f7: fix PLL clock division factorPatrice Chotard2017-11-171-7/+9
* stm32: fix STMicroelectronics copyrightPatrice Chotard2017-11-062-4/+5
* rockchip: rk3399: init CPU clock when rkclk_init()Kever Yang2017-11-011-78/+79
* dm: clk: fix PWR_CR3 register's bit 2 namePatrice Chotard2017-10-161-4/+4
* dm: clk: remove CLK() macro for clk_stm32h7Patrice Chotard2017-10-161-115/+108
* clk: uniphier: add NAND controller clockMasahiro Yamada2017-10-151-0/+12
* clk: uniphier: add PXs3 clock dataMasahiro Yamada2017-10-153-0/+23
* clk: uniphier: rework for better clock tree structureMasahiro Yamada2017-10-154-183/+323
* Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2017-10-101-1/+77
|\
| * clk: rmobile: Add RPC hyperflash clockMarek Vasut2017-09-241-1/+43
| * clk: rmobile: Add support for setting SDxCKCRMarek Vasut2017-09-241-0/+34
* | treewide: replace with error() with pr_err()Masahiro Yamada2017-10-046-17/+17
* | rockchip: rk322x: fix pd_bus hclk/pclkKever Yang2017-10-011-3/+3
* | rockchip: clk: fix typo in rk322x clock driverKever Yang2017-10-011-1/+1
* | rockchip: clk: Add rk3399 SARADC clock supportDavid Wu2017-10-011-1/+35
* | rockchip: clk: Add rk3368 SARADC clock supportDavid Wu2017-10-011-0/+32
* | rockchip: clk: Add rk3328 SARADC clock supportDavid Wu2017-10-011-1/+34
* | rockchip: clk: Add SARADC clock support for rk3288David Wu2017-10-011-0/+41
* | rockchip: clk: Add rv1108 SARADC clock supportDavid Wu2017-10-011-1/+32
* | dm: clk: add missing .priv_auto_alloc_size() for stm32f7Patrice Chotard2017-09-291-6/+7
|/
* dm: clk: add clk driver support for stm32h7 SoCsPatrice Chotard2017-09-222-0/+803
* rockchip: clk: rk3399: Convert to livetreePhilipp Tomsich2017-09-181-2/+2
* rockchip: clk: rk3399: add clk_enable function and support USB HOST0/1Philipp Tomsich2017-09-181-0/+15
* rockchip: clk: rk3368: Convert to livetreePhilipp Tomsich2017-09-181-1/+1
* dtoc: Put phandle args in an arraySimon Glass2017-09-151-1/+1
* dtoc: Rename the phandle structSimon Glass2017-09-151-1/+1
* dtoc: Add support for 32 or 64-bit addressesSimon Glass2017-09-152-3/+3
* clk: at91: utmi: Set the reference clock frequencyWenyou Yang2017-09-143-3/+83
* clk: Kconfig: Add dependences of SPL_CLKWenyou Yang2017-09-141-1/+1
* clk: uniphier: add System clock supportMasahiro Yamada2017-08-304-0/+67
* clk: rmobile: Split R8A7795 and R8A7796 core clock tablesMarek Vasut2017-08-261-33/+96
* ARM: uniphier: remove sLD3 SoC supportMasahiro Yamada2017-08-202-6/+0
* clk: uniphier: fix unmet direct dependencies warningMasahiro Yamada2017-08-201-3/+2
* rockchip: clk: remove RATE_TO_DIVKever Yang2017-08-137-29/+20
* rockchip: clk: update dwmmc clock divKever Yang2017-08-136-19/+26
* rockchip: clk: rk3368: add support for configuring the SPI clocksPhilipp Tomsich2017-08-131-26/+107
* rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate()Philipp Tomsich2017-08-131-1/+1
* rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clockPhilipp Tomsich2017-08-131-2/+17
* rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)Philipp Tomsich2017-08-131-6/+7
View Lorry Controller Status