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path: root/drivers/clk
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* rockchip: clock: rk3036: some fix according TRMKever Yang2017-06-071-9/+9
* rockchip: rk3036: clean mask definition for cru regKever Yang2017-06-071-45/+34
* rockchip: rk3368: Add clock driverAndy Yan2017-06-072-0/+292
* dm: clk: fixed: Update to support livetreeSimon Glass2017-06-011-3/+2
* dm: clk: Update uclass to support livetreeSimon Glass2017-06-012-11/+8
* clk: Modify xlate() method for livetreeSimon Glass2017-06-014-7/+7
* dm: core: Update device_bind_driver_to_node() to use ofnodeSimon Glass2017-06-011-1/+1
* dm: core: Replace of_offset with accessor (part 2)Simon Glass2017-06-011-1/+1
* dm: Rename dev_addr..() functionsSimon Glass2017-06-0110-13/+13
* dm: Use dm.h header when driver mode is usedSimon Glass2017-06-0114-16/+14
* Merge git://git.denx.de/u-boot-rockchipTom Rini2017-05-105-7/+161
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| * rockchip: clk: rk3399: allow requests for HDMI clocksPhilipp Tomsich2017-05-101-0/+7
| * rockchip: clk: rk3399: allow requests for PCLK_EFUSE1024NSPhilipp Tomsich2017-05-101-0/+4
| * rockchip: clk: rk3399: adapt MMC clk configuration to the updated RK3399 DTSPhilipp Tomsich2017-05-101-0/+4
| * rockchip: clk: rk3399: fix off-by one during rate calculation in i2c/spi_set_...Philipp Tomsich2017-05-101-3/+2
| * rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5Philipp Tomsich2017-05-101-6/+109
| * rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMCXu Ziyuan2017-05-101-0/+8
| * rockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIOXu Ziyuan2017-05-101-0/+12
| * rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIOXu Ziyuan2017-05-101-0/+12
| * rockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIOXu Ziyuan2017-05-101-0/+5
* | dm: clk: add BCM6345 clock driverÁlvaro Fernández Rojas2017-05-103-0/+87
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* clk: at91: Align the at91 pmc's compatiblesWenyou Yang2017-05-091-0/+6
* clk: at91: Align clk-master compatibles with kernelWenyou Yang2017-05-091-0/+1
* clk: at91: Enhance the peripheral clockWenyou Yang2017-05-091-3/+26
* aspeed: Refactor SCU to use consistent mask & shiftmaxims@google.com2017-05-081-20/+19
* aspeed: Add support for Clocks needed by MACsmaxims@google.com2017-05-081-31/+234
* aspeed: Add P-Bus clock in ast2500 clock drivermaxims@google.com2017-05-081-0/+11
* aspeed: Make SCU lock/unlock functions part of SCU APImaxims@google.com2017-05-081-16/+2
* stm32f7: use stm32f7 gpio driver supporting driver modelVikas Manocha2017-05-081-39/+0
* rockchip: clk: rk3399: 24MHz is not a power of 2Philipp Tomsich2017-04-041-2/+2
* rockchip: clk: rk3399: add clocking support for EthernetPhilipp Tomsich2017-04-041-0/+4
* rockchip: clk: rk3399: fix warnings for unused variables in SPL/non-SPLPhilipp Tomsich2017-04-041-0/+5
* rockchip: clk: rk3188: Allow configuration of the armclkHeiko Stübner2017-04-041-0/+63
* Merge git://git.denx.de/u-boot-rockchipTom Rini2017-03-176-10/+1196
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| * rockchip: rk3328: add clock driverKever Yang2017-03-162-0/+582
| * rockchip: rk3188: Add clock driverHeiko Stübner2017-03-162-0/+528
| * rockchip: clk: rk3288: limit gpll and cpll init to SPL buildHeiko Stübner2017-03-161-0/+2
| * dm: allow limiting pre-reloc markings to spl or tplHeiko Stübner2017-03-161-1/+2
| * rockchip: clk: rk3399: update driver for splKever Yang2017-03-161-9/+82
* | stm32f7: clk: remove usart1 clock enable from board initVikas Manocha2017-03-171-3/+0
* | clk: stm32f7: add clock driver for stm32f7 familyVikas Manocha2017-03-172-1/+333
* | clk: zynq: Add optional ethernet emio clock source supportStefan Herbrechtsmeier2017-02-171-0/+29
* | clk: zynq: Add zynq clock framework driverStefan Herbrechtsmeier2017-02-173-0/+468
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* Merge git://git.denx.de/u-boot-dmTom Rini2017-02-085-10/+11
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| * dm: core: Replace of_offset with accessorSimon Glass2017-02-085-10/+11
* | aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculationmaxims@google.com2017-02-081-2/+2
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* clk: uniphier: fix compatible strings for Pro5, PXs2, LD20 SD clockMasahiro Yamada2017-01-291-3/+3
* aspeed: Add basic ast2500-specific drivers and configurationmaxims@google.com2017-01-283-0/+274
* clk: zynqmp: Add clock driver support for zynqmpSiva Durga Prasad Paladugu2017-01-103-0/+249
* rockchip: clk: Support setting ACLKSimon Glass2016-11-251-0/+7