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path: root/drivers/clk/altera/clk-arria10.c
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* dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass2020-12-131-9/+9
* dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass2020-12-131-2/+2
* dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass2020-12-131-7/+7
* dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass2020-12-131-1/+1
* dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass2020-12-131-1/+1
* treewide: convert devfdt_get_addr() to dev_read_addr()Masahiro Yamada2020-07-251-1/+1
* Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini2020-07-241-1/+1
* treewide: convert devfdt_get_addr() to dev_read_addr()Masahiro Yamada2020-07-201-1/+1
* common: Drop linux/bitops.h from common headerWIP/2020-05-18-reduce-size-of-common.hSimon Glass2020-05-181-0/+1
* dm: core: remove the duplicated function dm_ofnode_pre_relocPatrick Delaunay2020-04-161-1/+1
* clk: socfpga: Read the clock parent's register base in probe functionWIP/05Apr2020Chee Hong Ang2020-04-051-22/+18
* dm: core: Create a new header file for 'compat' featuresSimon Glass2020-02-051-0/+2
* dm: core: Require users of devres to include the headerSimon Glass2020-02-051-0/+1
* clk: socfpga: replace dm_fdt_pre_reloc by dm_ofnode_pre_relocPatrick Delaunay2019-04-111-1/+2
* clk: Remove DM_FLAG_PRE_RELOC flag in various driversBin Meng2018-11-141-1/+0
* clk: socfpga: Add initial Arria10 clock driverMarek Vasut2018-08-131-0/+363
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