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path: root/drivers/clk/Kconfig
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* clk: Add Actions Semi OWL clock supportManivannan Sadhasivam2018-07-091-0/+1
| | | | | | | | | This commit adds Actions Semi OWL family base clock and S900 SoC specific clock support. For S900 peripheral clock support, only UART clock has been added for now. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* driver: clk: Add support for clocks on Armada 37xxMarek Behún2018-05-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | The drivers are based on Linux driver by Gregory Clement. The TBG clocks support only the .get_rate method. - since setting rate is not supported, the driver computes the rates when probing and so subsequent calls to the .get_rate method do not read the corresponding registers again The peripheral clocks support methods .get_rate, .enable and .disable. - the .set_parent method theoretically could be supported on some clocks (the parent would have to be one of the TBG clocks) - the .set_rate method would have to try all the divider values to find the best approximation of a given rate, and it doesn't seem like this should be needed in U-Boot, therefore not implemented Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* clk: Add ICS8N3QV01 driverMario Six2018-05-081-0/+8
| | | | | | Add a driver for the ICS8N3QV01 Quad-Frequency Programmable VCXO. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* clk: add driver for stm32mp1Patrick Delaunay2018-03-191-0/+8
| | | | | | | | | add RCC clock driver for STMP32MP157 - base on driver model = UCLASS_CLK - support ops to enable, disable and get rate of all SOC clock needed by U-Boot Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* ARC: clk: introduce HSDK CGU clock driverEugeniy Paltsev2017-12-111-0/+6
| | | | | | | | | | | | | | Synopsys HSDK clock controller generates and supplies clocks to various controllers and peripherals within the SoC. Each clock has assigned identifier and client device tree nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device tree sources. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.cPatrice Chotard2017-11-291-0/+8
| | | | | | | | | | Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs rename it to a more generic clk_stm32f.c Fix also some checkpatch errors/warnings. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
* clk: Kconfig: Add dependences of SPL_CLKWenyou Yang2017-09-141-1/+1
| | | | | | | The SPL_CLK config should depend on SPL && SPL_DM. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* spl: dm: Kconfig: split CLK support for SPL and TPLPhilipp Tomsich2017-08-131-0/+10
| | | | | | | | | Introduce TPL_CLK to allow finer-grained selection of TPL features for feature-rich (i.e. DM-based) TPL stages. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* spl: dm: Kconfig: SPL_CLK depends on SPL_DMPhilipp Tomsich2017-08-131-1/+1
| | | | | | | | | SPL_CLK should also depend on SPL_DM (and not just on CLK). Add the additional dependency. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* clk: rmobile: Add RCar Gen3 clock driverMarek Vasut2017-08-031-0/+1
| | | | | | | | | | | Add clock driver for the RCar Gen3 R8A7795 and R8A7796 SoCs . This driver allows reading out the clock configuration set by previous boot stages and enabling and disabling clock using the MSTP registers. Setting clock is not supported thus far. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* dm: clk: add BCM6345 clock driverÁlvaro Fernández Rojas2017-05-101-0/+8
| | | | | | | This is a simplified version of linux/arch/mips/bcm63xx/clk.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: zynq: Add zynq clock framework driverStefan Herbrechtsmeier2017-02-171-0/+8
| | | | | | | | | | | Add a clock framework driver for the zynq platform. The driver is based on the platform zynq clock driver but reworked to use static functions instead of run-time generated objects even for unused clocks. Additionally the CONFIG_ZYNQ_PS_CLK_FREQ is replaced by the ps-clk-frequency from the device tree. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* clk: zynqmp: Add clock driver support for zynqmpSiva Durga Prasad Paladugu2017-01-101-0/+7
| | | | | | | | | Add basic clock driver support for zynqmp which sets the required clock for GEM controller Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: boston: Providea simple driver for Boston board clocksPaul Burton2016-09-211-0/+8
| | | | | | | | | | Add a simple driver for the clocks provided by the MIPS Boston development board. The system provides information about 2 clocks whose rates are fixed by the bitfile flashed in the boards FPGA, and this driver simply reads the rates of these 2 clocks. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-08-151-0/+1
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| * clk: at91: Add clock driverWenyou Yang2016-08-151-0/+1
| | | | | | | | | | | | | | | | The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | clock: add Tegra186 clock driverStephen Warren2016-08-151-0/+1
|/ | | | | | | | | | | | In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. A tegra/ sub-directory is created to follow the existing pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* clk: exynos: add clock driver for Exynos7420 SocThomas Abraham2016-05-251-0/+1
| | | | | | | | | | | | Add a clock driver for Exynos7420 SoC. There are about 25 clock controller blocks in Exynos7420 out of which support for topc, top0 and peric1 blocks are added in this initial version of the driver. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* clk: uniphier: add Media I/O clock driver for UniPhier SoCsMasahiro Yamada2016-02-141-0/+2
| | | | | | | This is the initial commit for the UniPhier clock drivers. Currently, only the Media I/O clock is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* clk: move Kconfig options into sub-menuMasahiro Yamada2016-01-201-0/+4
| | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* clk: rename CONFIG_SPL_CLK_SUPPORT to CONFIG_SPL_CLKMasahiro Yamada2015-08-181-1/+1
| | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: Add a clock uclassSimon Glass2015-07-211-0/+19
Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
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