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* phy: atheros: add device tree bindings and configMichael Walle2020-05-071-0/+35
| | | | | | | | | | | | | | | | | Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge git://git.denx.de/u-boot-usbWIP/05May2020Tom Rini2020-05-052-10/+108
|\ | | | | | | - MediaTek USB host support
| * dt-bindings: usb: mtk-xhci: Add binding for MediaTek xHCI host controllerChunfeng Yun2020-05-021-0/+40
| | | | | | | | | | | | | | | | Add dt-binding for MediaTek xHCI host controller Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
| * dt-bindings: phy-mtk-tphy: add properties of address mapping and clocksChunfeng Yun2020-05-021-10/+68
| | | | | | | | | | | | | | | | | | | | 1. add the address mapping related properties; 2. make "ref" clock optional, and add optional clock "da_ref"; 3. add the banks layout of TPHY V1 and V2; Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86WIP/04May2020Tom Rini2020-05-041-0/+10
|\ \ | | | | | | | | | - Support 64-bit U-Boot as the payload for coreboot x86
| * | x86: Add a 64-bit 'coreboot64' buildSimon Glass2020-05-041-0/+10
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Coreboot is a first-stage bootloader mostly used on x86 devices as an alternative to UEFI. Coreboot runs in 32-bit mode. U-Boot currently supports booting from coreboot as a second-stage bootloader, also in 32-bit mode. However it is useful to be able to run U-Boot in 64-bit mode. To do this we can have a 32-bit SPL which switches over the CPU and jumps to a 64-bit U-Boot proper. Add a new 'coreboot64' board for running 64-bit U-Boot from coreboot. This uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot. This allows running 64-bit EFI images on x86, for example, without needing a native U-Boot port for a board. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge tag 'u-boot-imx-20200502' of ↵Tom Rini2020-05-042-0/+320
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX for 2020.07 ---------------- - imxrt: fix LCD clock, fix doc - new board: Coral Dev - imx8: enable Cache in SPL. SNVS, update SCFW API - imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading - MX6ULL : is_imx6ull to include i.MX6ULZ - Net: add config to enable TXC delay Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914
| * | doc: ahab: Add encrypted boot documentation for i.MX8/8x devicesBreno Lima2020-05-012-0/+320
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add AHAB encrypted boot documentation for i.MX8/8x family devices covering the following topics: - How to encrypt and sign the 2nd container in flash.bin image. - How to encrypt and sign a standalone container image. Include a CSF example to encrypt 2nd container in flash.bin image. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Catia Han <yaqian.han@nxp.com> Signed-off-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | | Merge tag 'u-boot-rockchip-20200501' of ↵Tom Rini2020-05-041-1/+3
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - dts clean up to use -u-boot for px30, rk3399 boards - dts sycn from upstream kernel for rk3328, rk3399 - add rockchip rng driver - new board support: rk3328-roc-cc, rk3399-roc-pc,Nanopi M4 2GB
| * | rockchip: rk3328: Add support for ROC-RK3328-CC boardChen-Yu Tsai2020-05-011-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit card size development board based on the Rockchip RK3328 SoC, with: - 1/2/4 GB DDR4 DRAM - eMMC connector for optional module - micro SD card slot - 1 x USB 3.0 host port - 2 x USB 2.0 host port - 1 x USB 2.0 OTG port - HDMI video output - TRRS connector with audio and composite video output - gigabit Ethernet - consumer IR receiver - debug UART pins The ROC-RK3328-CC has the enable pin of the SD card power switch tied to GPIO_0_D6. This pin also has the function SDMMC0_PWREN, which is muxed by default. SDMMC0_PWREN is an active high signal controlled by the MMC controller, however the switch enable is active low, and pulled low (enabled) by default to make things work on boot. As such, we need to mux away from SDMMC0_PWREN and use GPIO to enable power to the card. The default GPIO state for the pin is pull-down and input, which doesn't require extra configuration when paired with the external pull-down and active low switch. Deal with this by enabling regulator support in SPL, and setting "u-boot,dm-spl" for the regulator and other device nodes needed for muxing the pin. The device tree file is synced from the Linux kernel next-20200324. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | doc: describe the analysis of crash dumpsHeinrich Schuchardt2020-05-013-0/+143
| |/ |/| | | | | | | | | | | Provide an overview of the analysis of U-Boot crash dumps. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
* | Merge tag 'efi-2020-07-rc2' of ↵Tom Rini2020-04-301-48/+62
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-07-rc2 This pull request contains bug fixes needed due to the merged changes for EFI secure boot. Patches are supplied to identify EFI system partitions.
| * | doc/efi: rework secure boot descriptionHeinrich Schuchardt2020-04-301-48/+62
| | | | | | | | | | | | | | | | | | | | | Ensure a uniform formatting. Some rephrasing. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | x86: Add documentation for the chain-load featureSimon Glass2020-04-301-0/+28
| | | | | | | | | | | | | | | | | | | | | Add a few notes about this feature, which is aimed for development. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | acpi: Add a binding for ACPI settings in the device treeSimon Glass2020-04-301-0/+36
|/ / | | | | | | | | | | | | | | | | | | Devices need to report various identifiers in the ACPI tables. Rather than hard-coding these in drivers it is typically better to put them in the device tree. Add a binding file to describe this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | doc: sphinx: refresh parse-headers.pl from LinuxHeinrich Schuchardt2020-04-271-2/+2
| | | | | | | | | | | | | | | | | | Copy parse-headers.pl from Linux kernel tree: * fix the parameter description %s/--man/--usage/ * fix a documentation reference Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | doc: specify that xelatex is used as Latex engineHeinrich Schuchardt2020-04-271-0/+2
|/ | | | | | Building the pdf documentation on readthedocs.org fails with pdflatex. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* doc: boards: add Cubieboard7 documentationAmit Singh Tomar2020-04-243-0/+125
| | | | | | | | This adds build and flash steps for Actions S700 based Cubieboard7 board. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
* Merge tag 'u-boot-stm32-20200424' of ↵WIP/24Apr2020Tom Rini2020-04-241-4/+4
|\ | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Solve stm32mp15 pinctrl dts issue (patch conflict in branches master and next) - Split device tree for DHCOR Som and AV 96 board - Update PLL4 setting in AV96 board - Enable bootd, iminfo, imxtract on DHCOM
| * ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 boardMarek Vasut2020-04-241-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AV96 is in fact an assembly of DH Electronics DHCOR SoM on top of an AV96 reference board. Split the DTs to reflect that and make sure to DHCOR SoM can be reused on other boards easily. It is also highly recommended to configure the board for the DHCOM make stm32mp15_dhcom_basic_defconfig make DEVICE_TREE=stm32mp15xx-dhcor-avenger96 as that permits reusing the board code for the DH components, like accessing and reading out the ethernet MAC from EEPROM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Change-Id: I7db47280d4eb0d668eb4e006355240271154f97f
* | doc: invalid doc link in rstFlatTable.pyHeinrich Schuchardt2020-04-241-2/+0
| | | | | | | | | | | | | | Remove an invalid documentation link in rstFlatTable.py. This synchronizes the file with Linux next-20200413. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | mkimage: fit_image: Add option to make fit header alignKever Yang2020-04-241-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The image is usually stored in block device like emmc, SD card, make the offset of image data aligned to block(512 byte) can avoid data copy during boot process. eg. SPL boot from FIT image with external data: - SPL read the first block of FIT image, and then parse the header; - SPL read image data separately; - The first image offset is the base_offset which is the header size; - The second image offset is just after the first image; - If the offset of imge does not aligned, SPL will do memcpy; The header size is a ramdon number, which is very possible not aligned, so add '-B size'to specify the align size in hex for better performance. example usage: ./tools/mkimage -E -f u-boot.its -B 0x200 u-boot.itb Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Punit Agrawal <punit1.agrawal@toshiba.co.jp> Reviewed-by: Tom Rini <trini@konsulko.com>
* | docs: Fix conf.py for Sphinx 2.0Jonathan Corbet2020-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | commit 3bc8088464712fdcb078eefb68837ccfcc413c88 upstream. Our version check in Documentation/conf.py never envisioned a world where Sphinx moved beyond 1.x. Now that the unthinkable has happened, fix our version check to handle higher version numbers correctly. Signed-off-by: Jonathan Corbet <corbet@lwn.net> [rebase for u-boot] Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | bootcount_ext: Add flag to enable/disable bootcountFrédéric Danis2020-04-241-0/+51
|/ | | | | | | | | | | | | | | After a successful upgrade, multiple problem during boot sequence may trigger the altbootcmd process. This patch adds a version and an upgrade_available entries to the bootcount file to enable/disable the bootcount check. When failing to read the bootcount file it will consider that bootcount is enabled, acting as previously, and update the file accordingly. The bootcount file is only saved when `upgrade_available` is true, this allows to save writes to the filesystem. Signed-off-by: Frédéric Danis <frederic.danis@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* riscv: qemu: Remove the simple-bus driver for the SoC nodeBin Meng2020-04-231-1/+1
| | | | | | | | | | | | | Prior to QEMU v3.1.0, QEMU generated the 'virt' SoC node with a "riscv-virtio-soc" compatible string, and a "simple-bus" driver was created to accommodate that special case in U-Boot. Starting from QEMU v3.1.0, the SoC node was set as a "simple-bus", hence the special simple-bus driver is no longer needed. Update the doc to mention the latest tested QEMU version 4.2.0. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* doc: fix references to driver-modelHeinrich Schuchardt2020-04-171-1/+1
| | | | | | | Fix some errors pointed out by 'make refcheckdocs'. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* image: Add compressed Image parsing support in booti.Atish Patra2020-04-172-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | | Add compressed Image parsing support so that booti can parse both flat and compressed Image to boot Linux. Currently, it is difficult to calculate a safe address for every board where the compressed image can be decompressed. It is also not possible to figure out the size of the compressed file as well. Thus, user need to set two additional environment variables kernel_comp_addr_r and filesize to make this work. Following compression methods are supported for now. lzma, lzo, bzip2, gzip. lz4 support is not added as ARM64 kernel generates a lz4 compressed image with legacy header which U-Boot doesn't know how to parse and decompress. Tested on HiFive Unleashed and Qemu for RISC-V. Tested on Qemu for ARM64. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Fix minor rST formatting problems] Signed-off-by: Tom Rini <trini@konsulko.com>
* doc: spl: update reference to driver-model/README.txtPatrick Delaunay2020-04-171-1/+1
| | | | | | | | | | | Update the reference in doc/README.SPL to a no more existing file: "driver-model/README.txt", it is changed to "doc/driver-model/design.rst". Adding the directory path /doc/ allows to check this reference with 'make refcheckdocs'. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* doc: device-tree-bindings: update reference to binding directoryPatrick Delaunay2020-04-161-1/+1
| | | | | | | | | Update reference in files detected by scripts/documentation-file-ref-check doc/devicetree/device-tree-bindings/ => doc/device-tree-bindings/ Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* doc: update reference to README.imximagePatrick Delaunay2020-04-161-1/+1
| | | | | | | | | Update reference in many files detected by scripts/documentation-file-ref-check README.imximage => imx/mkimage/imximage.txt Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* dt-bindings: gpio: alignment with kernel v5.3Patrick Delaunay2020-04-162-126/+196
| | | | | | | | | | | | Update the binding file for gpio, it is just an alignment with kernel v5.3. The U-Boot code example for gpio-hog (not directly linked to binding) is moved in a new file doc/README.gpio. [commit 21676b706e99 ("gpio: fixes for gpio-hog support") & 'commit 4762a9988ede ("gpio: add gpio-hog support")'] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dt-bindings: gpio: document the new pull-up/pull-down flagsPatrick Delaunay2020-04-161-0/+24
| | | | | | | | | | | | | | | This commit extends the flags that can be used in GPIO specifiers to indicate if a pull-up resistor or pull-down resistor should be enabled. It is the backport of linux commit ede033e1e863c ('dt-bindings: gpio: document the new pull-up/pull-down flags') from Thomas Petazzoni <thomas.petazzoni@bootlin.com> and integrated in v5.1-rc1 https://github.com/torvalds/linux/commit/ede033e1e863c Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge tag 'efi-2020-07-rc1' of ↵WIP/16Apr2020Tom Rini2020-04-162-0/+89
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-07-rc1 This pull request * provides an implementation of UEFI secure booting * fixes a problem with the rsa_mod_exp driver which stops some boards from booting when CONFIG_RSA is enabled which is needed for UEFI secure booting * enables the EFI_RNG_PROTOCOL if DM_RNG is enabled * fixes some function comments
| * efi_loader: add some description about UEFI secure bootAKASHI Takahiro2020-04-161-0/+77
| | | | | | | | | | | | | | | | A small text in docs/uefi/uefi.rst was added to explain how we can configure and utilise UEFI secure boot feature on U-Boot. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
| * efi_loader: function descriptions efi_watchdog.cHeinrich Schuchardt2020-04-161-0/+6
| | | | | | | | | | | | | | Correct function descriptions in efi_watchdog.c. Add the descriptions to the generated HTML documentation. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi_loader: function descriptions efi_unicode_collation.cHeinrich Schuchardt2020-04-161-0/+6
| | | | | | | | | | | | | | Correct function descriptions in efi_unicode_collation.c Add the Unicode collation protocol to the generated HTML documentation. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | Merge tag 'dm-pull-10apr20-take2' of git://git.denx.de/u-boot-dmTom Rini2020-04-163-30/+79
|\ \ | | | | | | | | | | | | | | | | | | | | | Functions for reading indexed values from device tree Enhancements to 'dm' command Log test enhancements and syslog driver DM change to read parent ofdata before children Minor fixes
| * | dm: core: Read parent ofdata before childrenSimon Glass2020-04-161-24/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present a device can read its ofdata before its parent has done the same. This can cause problems in the case where the parent has a 'ranges' property, thus affecting the operation of dev_read_addr(), for example. We already probe parent devices before children so it does not seem to be a large step to do the same with ofdata. Make the change and update the documentation in this area. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | doc: driver-model: there is no UCLASS_ETHERNETHeinrich Schuchardt2020-04-161-1/+1
| | | | | | | | | | | | | | | | | | | | | %s/UCLASS_ETHERNET/UCLASS_ETH/g Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | log: syslog driverHeinrich Schuchardt2020-04-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a log driver that broadcasts RFC 3164 messages to syslog servers. rsyslog is one implementation of such a server. The messages are sent to the local broadcast address 255.255.255.255 on port 514. The environment variable log_hostname can be used to provide the HOSTNAME field for the messages. The optional TIMESTAMP field of RFC 3164 is not provided. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | sandbox: Update PCI nodes in dts filesTom Rini2020-04-161-5/+5
| |/ | | | | | | | | | | | | | | | | | | | | The way the PCI nodes are written today causes a number of warnings if we stop disabling some of the warnings we pass to DTC. As these warnings aren't disabled in current Linux Kernel builds, we should aim to not disable them here either, so rewrite these slightly. Update the driver model doc as well. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | dts: Add a binding for hid-over-i2cSimon Glass2020-04-161-0/+44
| | | | | | | | | | | | | | Add this binding from Linux v5.4. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: pci: Allow disabling auto-config for a deviceSimon Glass2020-04-161-0/+23
| | | | | | | | | | | | | | | | Add a means to avoid configuring a device when needed. Add an explanation of why this is useful to the binding file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | tpm: cr50: Use the correct GPIO bindingSimon Glass2020-04-162-2/+2
|/ | | | | | | This device should use ready-gpios rather than ready-gpio. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'next'Tom Rini2020-04-1310-11/+263
|\ | | | | | | | | | | | | | | | | | | | | Pull in changes that have been pending in our 'next' branch. This includes: - A large number of CI improvements including moving to gcc-9.2 for all platforms. - amlogic, xilinx, stm32, TI SoC updates - USB and i2c subsystem updtaes - Re-sync Kbuild/etc logic with v4.19 of the Linux kernel. - RSA key handling improvements
| * sandbox: Add documentation about required/useful packagesSimon Glass2020-04-101-0/+10
| | | | | | | | | | | | | | Quite a few packages are used by sandbox or tools. Add a list of these to help people setting up for the first time. Signed-off-by: Simon Glass <sjg@chromium.org>
| * Merge tag 'xilinx-for-v2020.07' of ↵WIP/07Apr2020-nextTom Rini2020-04-073-21/+30
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2020.07 common: - Align ENV_FAT_INTERFACE - Fix MAC address source print log - Improve based autodetection code xilinx: - Enable netconsole Microblaze: - Setup default ENV_OFFSET/ENV_SECT_SIZE Zynq: - Multiple DT updates/fixes - Use DEVICE_TREE environment variable for DTB selection - Switch to single zynq configuration - Enable NOR flash via DM - Minor SPL print removal - Enable i2c mux driver ZynqMP: - Print multiboot register - Enable cache commands in mini mtest - Multiple DT updates/fixes - Fix firmware probing when driver is not enabled - Specify 3rd backup RAM boot mode in SPL - Add SPL support for zcu102 v1.1 and zcu111 revA - Redesign debug uart enabling and psu_init delay - Enable full u-boot run from EL3 - Enable u-boot.itb generation without ATF with U-Boot in EL3 Versal: - Enable distro default - Enable others SPI flashes - Enable systems without DDR Drivers: - Gem: - Flush memory after freeing - Handle mdio bus separately - Watchdog: - Get rid of unused global data pointer - Enable window watchdog timer - Serial: - Change reinitialization logic in zynq serial driver Signed-off-by: Tom Rini <trini@konsulko.com>
| | * ARM: zynq: Switch to single zynq configurationsMichal Simek2020-04-061-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a lot of zynq configurations which can be merged together and use only one for all. The similar change has been done for ZynqMP by commit be1b6c32d940 ("arm64: zynqmp: Use zynqmp_virt platform") Build SPL with u-boot.img for zc706 like this. export DEVICE_TREE=zynq-zc706 && make xilinx_zynq_virt_defconfig && make -j8 u-boot.img is generic for all boards. Tested on Zybo, zc702, zc706, zc770-xm011-x16, cc108 and microzed. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ram: stm32mp1: the property st, phy-cal becomes optionalPatrick Delaunay2020-03-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This parameter "st,phy-cal" becomes optional and when it is absent the built-in PHY calibration is done. It is the case in the helper dtsi file "stm32mp15-ddr.dtsi" except if DDR_PHY_CAL_SKIP is defined. This patch also impact the ddr interactive mode - the registers of the param 'phy.cal' are initialized to 0 when "st,phy-cal" is not present in device tree (default behavior when DDR_PHY_CAL_SKIP is not activated) - the info 'cal' field can be use to change the calibration behavior - cal=1 => use param phy.cal to initialize the PHY, built-in training is skipped - cal=0 => param phy.cal is absent, built-in training is used (default) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
| * | stm32mp1: add 800 MHz profile supportPatrick Delaunay2020-03-241-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32MP1 series is available in 3 different lines which are pin-to-pin compatible: - STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD - STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD - STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz Each line comes with a security option (cryptography & secure boot) & a Cortex-A frequency option : - A : Cortex-A7 @ 650 MHz - C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz - D : Cortex-A7 @ 800 MHz - F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz This patch adds the support of STM32MP15xD and STM32MP15xF in U-Boot. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
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