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* Merge branch 'master' into nextTom Rini2023-03-271-1/+1
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| * configs: Resync with savedefconfigTom Rini2023-03-271-1/+1
| | | | | | | | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* | xilinx: Enable SMC command for arm64 targetsMichal Simek2023-03-091-0/+1
|/ | | | | | | | | SMC command is very useful for TF-A testing or issuing commands which are not covered by any driver. Strongly recommend to disable this command on any product unless it is required. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/23c77a2cbd083963ca17b84de4108dbb1f28597f.1676450712.git.michal.simek@amd.com
* configs: Resync with savedefconfigTom Rini2023-02-171-2/+2
| | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* arm64: zynqmp: enable gigadeviceVictor Lim2023-01-101-0/+1
| | | | | | | | enabling gigadevice in the related files Signed-off-by: Victor Lim <vlim@gigadevice.com> Link: https://lore.kernel.org/r/20230109234946.14540-4-vlim@gigadevice.com Signed-off-by: Michal Simek <michal.simek@amd.com>
* Convert CONFIG_THOR_RESET_OFF to KconfigTom Rini2022-12-221-0/+1
| | | | | | | This converts the following to Kconfig: CONFIG_THOR_RESET_OFF Signed-off-by: Tom Rini <trini@konsulko.com>
* xilinx: Remove unused ZYNQ_MAC_IN_EEPROM/ZYNQ_GEM_I2C_MAC_OFFSET entriesMichal Simek2022-12-051-2/+0
| | | | | | | | | | The commit ba74bcf3e07b ("xilinx: common: Remove zynq_board_read_rom_ethaddr()") removed zynq_board_read_rom_ethaddr() because xlnx,eeprom link via DT chosen node is no longer used. But forget to remove Kconfig entries which are used by this code only. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/f97451ed33409838efea4071553b6da795cfc578.1669192026.git.michal.simek@amd.com
* arm64: zynqmp: Disable watchdog by default for virt platformMichal Simek2022-11-221-2/+0
| | | | | | | | | Disable watchdog based on request in past that not all Linux rootfs have proper utilities ready to service it. Enable it if your rootfs have proper watchdog handling. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/62dfc08f32635abee42feab26aaa9efed52134c0.1665567328.git.michal.simek@amd.com
* Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASESimon Glass2022-10-311-1/+1
| | | | | | | | | The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE and this makes it imposible to use CONFIG_VAL(). Rename it to resolve this problem. Signed-off-by: Simon Glass <sjg@chromium.org>
* video: Rename CONFIG_DM_VIDEO to CONFIG_VIDEOSimon Glass2022-10-301-1/+1
| | | | | | | Now that all the old code is gone, rename this option. Driver model migration is now complete. Signed-off-by: Simon Glass <sjg@chromium.org>
* treewide: Stop enabling CONFIG_LCDSimon Glass2022-10-301-1/+0
| | | | | | | This option is not used anymore since the LCD implementation is being removed. Stop enabling it on various boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* xilinx: Enable CMD_GREPENV/SETEXPR by defaultMichal Simek2022-09-131-0/+1
| | | | | | | | Enable both of these commands in Xilinx SoCs to be able to use them in boot scripts. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1a612be7e09e9bc502f30e1f025441ccf8accba5.1661340513.git.michal.simek@amd.com
* xilinx: Add env redund offsetT Karthik Reddy2022-09-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | ENV_OFFSET_REDUND config is by default set to 0 for flashes. Saving the env variables is overwriting data at 0 offset, which is wrong. So add default redund env offset for Zynq, ZynqMP, Versal and microblaze platforms. Configured ENV_OFFSET_REDUND offsets by ENV_OFFSET + (2 * ENV_SIZE). In case of versal, we configured ENV_OFFSET_REDUND at 0x7F00000 instead of 0x7F80000. As BOOT_SCRIPT_OFFSET is already configured at 0x7F80000. Added ENV_OFFSET_REDUND in Kconfig for microblaze due to dependency of ENV_IS_IN_SPI_FLASH config. Below table specifies platform specific env and env redund offsets. PLAT ENV_OFFSET ENV_OFFSET_REDUND ---- ---------- ----------------- ZYNQ 0xE0000 0xE40000 ZYNQMP 0x1E00000 0x1E80000 VERSAL 0x7F40000 0x7F00000 MICROBLAZE 0x1080000 0x10C0000 Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/92656dc08f0f5a749d62b71ca6e77fe1be72e9e0.1661340204.git.michal.simek@amd.com
* arm64: zynqmp: Enable power domain driverAshok Reddy Soma2022-07-261-0/+2
| | | | | | | | | Enable power domain driver to configure pmufw config object and request node for all the IP's that are enabled in DT. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20220722084658.30995-4-ashok.reddy.soma@xilinx.com
* arm64: zynqmp: Enable reset driverAshok Reddy Soma2022-07-261-0/+2
| | | | | | | | | | Enable reset driver for ZynqMP platforms. This will enable us to reset the IP's using generic reset_assert and reset_deassert calls. Signed-off-by: T Karthik Reddy <t.karthik.reddy@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220720095959.29610-4-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
* arm64: zynqmp: Enable SLG gpo driver by defaultMichal Simek2022-07-261-0/+1
| | | | | | | This device is used on SOM CCs that's why enable it by default. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/ebbfc0c883ca7d4f70c75d8d3655aaa6a81d77be.1656943737.git.michal.simek@amd.com
* xilinx: zynqmp: Do not use 0 as spl bss start addressStefan Herbrechtsmeier2022-07-261-2/+0
| | | | | | | | | | Do not use 0 as address for memory because of the special meaning for pointers (null pointer). Change the spl bss start address to the second page. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220714134733.7487-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
* Convert CONFIG_SYS_BOOTM_LEN to KconfigTom Rini2022-07-071-0/+1
| | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SYS_BOOTM_LEN As part of this, rework error handling in boot/bootm.c so that we pass the buffer size to handle_decomp_error as CONFIG_SYS_BOOTM_LEN will not be available to host tools but we do know the size that we passed to malloc(). Cc: Soeren Moch <smoch@web.de> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'xilinx-for-v2022.10' of ↵Tom Rini2022-06-271-0/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
| * xilinx: Enable support for SquashFSMichal Simek2022-06-271-0/+1
| | | | | | | | | | | | | | Enable SquashFS for all xilinx platforms. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/dbe85afda8cd90ebfc537979d382808ff9bec160.1655982259.git.michal.simek@amd.com
| * xilinx: Add CONFIG_DM_ETH_PHY configT Karthik Reddy2022-06-241-0/+1
| | | | | | | | | | | | | | | | | | | | Enable CONFIG_DM_ETH_PHY to utilize shared MDIO bus support on all xilinx platforms. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/965981eb324d13a98aad8bd88eb8b50bc5147a7e.1652181968.git.michal.simek@amd.com
* | Convert CONFIG_SYS_SPL_ARGS_ADDR to KconfigTom Rini2022-06-061-0/+1
| | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SYS_SPL_ARGS_ADDR In doing so, we also consistently use this variable for SPL_OS_BOOT and not CONFIG_SYS_FDT_BASE in some cases. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Convert CONFIG_SYS_SPL_MALLOC_SIZE et al to KconfigTom Rini2022-06-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_SPL_MALLOC_START We introduce a default value here as well, and CONFIG_SYS_SPL_MALLOC to control if we have a malloc pool or not. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Convert CONFIG_SPL_BSS_START_ADDR to KconfigTom Rini2022-06-061-0/+2
| | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SPL_BSS_START_ADDR Signed-off-by: Tom Rini <trini@konsulko.com>
* | Convert CONFIG_SPL_STACK to KconfigTom Rini2022-06-061-0/+2
| | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SPL_STACK Signed-off-by: Tom Rini <trini@konsulko.com>
* | Convert CONFIG_SPL_BSS_MAX_SIZE et al to KconfigTom Rini2022-06-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SPL_BSS_MAX_SIZE CONFIG_SPL_MAX_FOOTPRINT Note that the da850evm platforms were violating the "only use one" rule here, and so now hard-code their BSS limit. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Convert CONFIG_SPL_PAD_TO et al to KconfigTom Rini2022-06-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE CONFIG_TPL_PAD_TO CONFIG_TPL_MAX_SIZE Note that we need to make TPL_MAX_SIZE be hex, and so move and convert the existing places. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Convert CONFIG_SPL_FS_LOAD_PAYLOAD_NAME et al to KconfigTom Rini2022-06-061-0/+2
| | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SPL_FS_LOAD_ARGS_NAME CONFIG_SPL_FS_LOAD_KERNEL_NAME CONFIG_SPL_FS_LOAD_PAYLOAD_NAME Signed-off-by: Tom Rini <trini@konsulko.com>
* | Convert CONFIG_SYS_PBSIZE to KconfigTom Rini2022-06-061-0/+1
| | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SYS_PBSIZE Signed-off-by: Tom Rini <trini@konsulko.com>
* | Convert CONFIG_SYS_MAXARGS to KconfigTom Rini2022-06-061-0/+1
|/ | | | | | | This converts the following to Kconfig: CONFIG_SYS_MAXARGS Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: Resync with savedefconfigTom Rini2022-04-201-1/+0
| | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: Resync with savedefconfigTom Rini2022-04-081-1/+1
| | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'xilinx-for-v2022.07-rc1-v2' of ↵Tom Rini2022-04-051-0/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.07-rc1 v2 xilinx: - Allow booting bigger kernels till 100MB zynqmp: - DT updates (reset IDs) - Remove unneeded low level uart initialization from psu_init* - Enable PWM features - Add support for 1EG device serial_zynq: - Change fifo behavior in DEBUG mode zynq_sdhci: - Fix BASECLK setting calculation clk_zynqmp: - Add support for showing video clock gpio: - Update slg driver to handle DT flags net: - Update ethernet_id code to support also DM_ETH_PHY - Add support for DM_ETH_PHY in gem driver - Enable dynamic mode for SGMII config in gem driver pwm: - Add driver for cadence PWM versal: - Add support for reserved memory firmware: - Handle PD enabling for SPL - Add support for IOUSLCR SGMII configurations include: - Sync phy.h with Linux - Update xilinx power domain dt binding headers
| * arm: zynqmp: Enable PWM command and cadence ttc pwm driverMichal Simek2022-03-301-0/+3
| | | | | | | | | | | | | | Enable PWM ttc driver and command in generic image. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/a660c8f2010f4f07534753e0ac44a34b8ff0d3c3.1634303847.git.michal.simek@xilinx.com
* | configs: Resync with savedefconfigTom Rini2022-04-011-2/+2
| | | | | | | | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* | Convert CONFIG_CLOCKS to KconfigTom Rini2022-04-011-0/+1
|/ | | | | | | This converts the following to Kconfig: CONFIG_CLOCKS Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_SYS_FAULT_ECHO_LINK_DOWN to KconfigTom Rini2022-03-251-0/+1
| | | | | | | | This converts the following to Kconfig: CONFIG_SYS_FAULT_ECHO_LINK_DOWN Cc: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'xilinx-for-v2022.07-rc1' of ↵Tom Rini2022-03-161-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.07-rc1 microblaze: - Add support for reserved memory xilinx: - Update FRU code with MAC reading zynqmp: - Remove double AMS setting - DT updates (mostly for SOMs) - Add support for zcu106 rev 1.0 zynq: - Update nand binding nand: - Aligned zynq_nand to upstream DT binding net: - Add support for ethernet-phy-id mmc: - Workaround CD in zynq_sdhci driver also for ZynqMP - Add support for dynamic/run-time SD config for SOMs gpio: - Add driver for slg7xl45106 firmware: - Add support for dynamic SD config power-domain: - Update zynqmp driver with the latest firmware video: - Add skeleton driver for DP and DPDMA i2c: - Fix i2c to work with QEMU pinctrl: - Add driver for zynqmp pinctrl driver
| * arm64: zynqmp: add support for zcu106 rev1.0Neal Frager2022-03-091-1/+1
| | | | | | | | | | | | | | | | | | This patch adds psu_init for Xilinx ZCU106 rev1.0. Xilinx ZCU106 rev1.0 has newer x16 DDR4 memories and it is SW compatible with revA. Signed-off-by: Neal Frager <neal.frager@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/997b3e23457e4d24ce0e197d742382aaec36c2b2.1646230318.git.michal.simek@xilinx.com
* | Convert CONFIG_BOOTP_MAY_FAIL et al to KconfigTom Rini2022-03-031-0/+2
|/ | | | | | | | | | | | This converts the following to Kconfig: CONFIG_BOOTP_MAY_FAIL CONFIG_BOOTP_VENDOREX CONFIG_BOOTP_BOOTFILESIZE CONFIG_BOOTP_NISDOMAIN CONFIG_BOOTP_TIMEOFFSET Cc: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'xilinx-for-v2022.04-rc3' of ↵Tom Rini2022-02-211-2/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.04-rc3 microblaze: - Fix exception handler zynqmp: - Show information about secure images - DT changes (som u-boot file removal) - Fix zynqmp_pm_cfg_obj_convert.py - Fix platform boot xilinx: - Fix bootm_size calculation - Remove GPIO_EXTRA_HEADER selection power: - Add zynqmp power management driver scsi: - Add phy support to ceva driver zynq qspi: - Fix unaligned accesses and check baudrate setup - Add support for spi memory operations net: - Fix 64bit calculation in axi_emac video: - Add missing gpio dependency for seps driver
| * arm64: zynqmp: Fix dependencies around ZYNQMP_PSU_INIT_ENABLEDMichal Simek2022-02-211-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | ZYNQMP_PSU_INIT_ENABLED is called only when BOARD_EARLY_INIT_F is defined that's why cover this dependency in Kconfig. board_early_init_f() is only part related to CONFIG_ZYNQMP_PSU_INIT_ENABLED which is disabled now that's why disable BOARD_EARLY_INIT_F and also build board_early_init_f() only when CONFIG_BOARD_EARLY_INIT_F is enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/d89253ec1590cd513dcd4bfbedebae618bd6d605.1645104518.git.michal.simek@xilinx.com
| * arm64: zynqmp: Build psu_spl_init for SPL all the timeMichal Simek2022-02-211-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | ZYNQMP_PSU_INIT_ENABLED specifically saying that has connection to full U-Boot not SPL that's why build psu_spl_init for SPL all the time. Also disable ZYNQMP_PSU_INIT_ENABLED because it ends up in situation that psu_init() is called twice which is wrong. By default only SPL should call it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/bf1e5d9a163f8853c7d951ad42965114ab0b1f50.1645104518.git.michal.simek@xilinx.com
| * xilinx: Enable OF_BOARD for zynq and zynqmp boardsMichal Simek2022-02-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The commit 985503439762 ("fdt: Don't call board_fdt_blob_setup() without OF_BOARD") forced to enable OF_BOARD for platforms which provide DT externally. Zynq/ZynqMP boards are using this feature for a long time that's why there is a need to enable it by default. Also code expects to return error in case of error that's why also fill it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/9f11bbffe2849f4da7d72712082d579262fe8fd8.1645104518.git.michal.simek@xilinx.com
* | configs: Resync with savedefconfigTom Rini2022-02-091-1/+1
| | | | | | | | | | | | | | Rsync all defconfig files using moveconfig.py and update scripts/pylint.base Signed-off-by: Tom Rini <trini@konsulko.com>
* | sata: Rearrange Kconfig for SATASimon Glass2022-02-091-0/+1
| | | | | | | | | | | | | | | | | | Move the SATA options inside an 'if SATA' part, so they are grouped. Fix the 'Complient' typo while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
* | Convert CONFIG_REMAKE_ELF to KconfigAlper Nebi Yasak2022-02-091-0/+1
|/ | | | | | | This converts the following to Kconfig: CONFIG_REMAKE_ELF Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
* configs: Resync with savedefconfigTom Rini2022-01-241-1/+0
| | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_ZYNQMP_PSU_INIT_ENABLED to KconfigTom Rini2021-12-271-0/+1
| | | | | | | This converts the following to Kconfig: CONFIG_ZYNQMP_PSU_INIT_ENABLED Signed-off-by: Tom Rini <trini@konsulko.com>
* Clarify CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW in KconfigTom Rini2021-12-271-1/+0
| | | | | | | | This is a "hex" prompt but the default value was given as an int. Switch the default to hex (0x0) and remove the defconfigs that were using the default, but as hex before. Signed-off-by: Tom Rini <trini@konsulko.com>
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