summaryrefslogtreecommitdiff
path: root/board
Commit message (Collapse)AuthorAgeFilesLines
* Tegra: common: add ft_board_setup supportBryan Wu2014-05-201-0/+127
| | | | | | | | | | | | | | | | | | ft_board_setup() provides a hook for U-Boot to overwrite some properties in DT file which will be passed to kernel. Tegra version of ft_board_setup() will firstly overwirte board info related serial numbers in DT file. Also update config files for Tegra as well. Bug 200005196 Bug 1482099 Change-Id: Ide208139618cab12d355dcc48a407e5ea62a31ee Signed-off-by: Bryan Wu <pengw@nvidia.com> Reviewed-on: http://git-master/r/411664 Reviewed-by: Winnie Hsu <whsu@nvidia.com>
* ARM: tegra: add warmboot support for Tegra124Bryan Wu2014-04-241-3/+6
| | | | Signed-off-by: Bryan Wu <pengw@nvidia.com>
* ARM: tegra: add Jetson TK1 boardStephen Warren2014-03-144-0/+263
| | | | | | | | | Jetson TK1 and Venice2 are very similar boards, at least as far as theHW components that U-Boot supports so far. Hence, add the Jetson TK1 board as a variant of the Venice2 board, so we don't have to duplicate any code or pinmux tables. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Tegra124 pinmux cleanupStephen Warren2014-03-141-167/+167
| | | | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra124_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. There are differences in the set of drive groups. I have validated this against the TRM. There are differences order of pin definitions in pinmux.c; these previously had significant mismatches with the correct order:-( I adjusted a few entries in pinmux-config-venice2.h since the set of legal functions for some pins was updated to match the TRM. Signed-off-by: Stephen Warren <swarren@nvidia.com> --- Sent V1
* ARM: tegra: Tegra114 pinmux cleanupStephen Warren2014-03-141-180/+180
| | | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra114_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. This introduces a few changes to pin/group/function naming and the set of available functions for each pin. The new values now exactly match the TRM; the chip documentation. I adjusted a few entries in pinmux-config-dalmore.h due to this. Signed-off-by: Stephen Warren <swarren@nvidia.com> --- Sent V1
* ARM: tegra: Tegra30 pinmux cleanupStephen Warren2014-03-142-473/+473
| | | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra30_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. This introduces a few changes to pin/group/function naming and the set of available functions for each pin. The new values now exactly match the TRM; the chip documentation. I adjusted one entry in pinmux-config-cardhu.h due to this. Signed-off-by: Stephen Warren <swarren@nvidia.com> --- Sent V1
* ARM: tegra: Tegra20 pinmux cleanupStephen Warren2014-03-147-33/+33
| | | | | | | | | | | | | | This renames all the Tegra20 pinmux pins and functions so they have a prefix which matches the type name. The entries in tegra20_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> --- Sent V1
* ARM: tegra: pinmux naming consistency fixesStephen Warren2014-03-148-90/+92
| | | | | | | | | | | | | | | Clean up the naming of pinmux-related objects: * Refer to drive groups rather than pad groups to match the Linux kernel. * Ensure all pinmux API types are prefixed with pmux_, values (defines) are prefixed with PMUX_, and functions prefixed with pinmux_. * Modify a few type names to make their content clearer. * Minimal changes to SoC-specific .h/.c files are made so the code still compiles. A separate per-SoC change will be made immediately following, in order to keep individual patch size down. Signed-off-by: Stephen Warren <swarren@nvidia.com> --- Sent V1
* ARM: tegra: prototype pinmux_init() in board.hStephen Warren2014-03-141-2/+6
| | | | | | | | | | pinmux_init() is a board-level function, not a pinmux driver function. Move the prototype to a board header rather than the driver header. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> --- Sent V1
* ARM: tegra: make all I2C ports open-drainStephen Warren2014-03-132-16/+16
| | | | | | | | | | | I2C protocol requires open-drain IOs. Fix the Dalmore and Venice2 pinmux tables to configure the IOs correctly. Without this, Tegra may actively drive the lines high while an external device is actively driving the lines low, which can only lead to bad things. Signed-off-by: Stephen Warren <swarren@nvidia.com> --- Sent V1
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-03-1018-22/+358
|\
| * arm: atmel: sama5d3: add nand spl boot supportBo Shen2014-03-091-0/+2
| | | | | | | | | | | | | | Add NAND SPL boot support with hardware PMECC. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: atmel: sama5d3: add spi spl boot supportBo Shen2014-03-091-0/+2
| | | | | | | | | | | | | | Add SPI SPL boot support for sama5d3xek board. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * ARM: atmel: add sama5d3 Xplained board supportBo Shen2014-03-092-0/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add sama5d3 Xplained board support which use Atmel SAMA5D36 SoC. Now it supports boot from NAND flash and SD/MMC card. Features support: - NAND flash - SD/MMC card - Two USB hosts - Ethernet (one GMAC, one EMAC) Signed-off-by: Bo Shen <voice.shen@atmel.com> [reorder boards.cfg] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * at91sam9263ek: add mmc supportAndreas Henriksson2014-03-091-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for using the Atmel MCI driver on at91sam9263ek. This change is modeled after the existing at91sam9260ek support. Please note that this hooks up slot1 (MCI1) for SD. Not both. Tested with at91bootstrap and u-boot on dataflash in slot 0 and fat-formatted 8GB SDHC in slot 1 on first revision at91sam9263ek (which must use dataflash in slot0 to boot). CONFIG_ATMEL_MCI_PORTB not tested. Signed-off-by: Andreas Henriksson <andreas.henriksson@endian.se> [remove empty line] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * board/BuR/common: fix phy addressesHannes Petermaier2014-03-061-2/+2
| | | | | | | | | | | | | | | | B&R boards are using Phy Addresses 'one' and 'two', prior this was defined through #define PHYADDR 1 within a header file. Now this is addresses are given with device-driver structure. Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
| * arm: am335x: DXR2: Reset SMSC LAN9303 switch via GPIO upon bootupStefan Roese2014-03-042-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | Since the switch may be re-configured for VLAN usage in Linux (or any other OS), lets reset the switch to its default register values upon power-up. Otherwise network might not be available in U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Roger Meier <r.meier@siemens.com> Cc: Lukas Stockmann <lukas.stockmann@siemens.com> Cc: Tom Rini <trini@ti.com>
| * ARM: AM43xx: Add Ethernet boot support to SPLMugunthan V N2014-03-041-2/+0
| | | | | | | | | | | | | | Add Ethernet Boot support to SPL Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * ARM: AM4372: Update EMIF registers for DDR3Lokesh Vutla2014-03-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating EMIF_PHY_CTRL and adding EMIF_READ_WRITE_EXECUTION_THRESHOLD registers. In EMIF_PHY_CTRL: Updating [4:0]READ_LATENCY to 8, because at higher frequencies like 400MHz the read latency expected will be CL+3 as per tests from HW folks. Clearing [19]PHY_DIS_CALIB_RST bit as this is used onl for debug purpose. With out this resume is not working(Still waiting for PHY team to come back for better explanation). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: DRA7xx: add support for reading cpsw 2nd mac from efuseMugunthan V N2014-03-041-0/+15
| | | | | | | | | | | | | | | | | | Adding support for reading cpsw 2nd mac address from efuse and pass it to kernel via dtb which will be used in dual emac mode of cpsw. Also correct the bit masking of mac id read from the efuse. Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * ARM: AM335x: add support for reading cpsw 2nd mac address from efuseMugunthan V N2014-03-041-0/+15
| | | | | | | | | | | | | | | | | | Adding support for reading cpsw 2nd mac address from efuse and pass it to kernel via dtb which will be used in dual emac mode of cpsw. Also adding mii command support to am335x common config. Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * ARM: AM43xx: Add CPSW support to AM43xx EPOS and GP EVMMugunthan V N2014-03-042-2/+142
| | | | | | | | | | | | | | | | Adding support for CPSW to AM43xx EPOS nad GP EVM which is connected to RMII and RGMII phy respectively and enable cpsw in config. Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * drivers: net: cpsw: add support to have phy address from cpsw platform dataMugunthan V N2014-03-0411-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | Some platforms like AM437x have different EVMs with different phy addresses, so this patch adds support for passing phy address via cpsw plaform data. Also renamed phy_id to phy_addr so better understanding of the code. Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [trini: Update BuR am335x_igep0033 pcm051_rev3 pcm051_rev1 cm_t335 pengwyn boards] Signed-off-by: Tom Rini <trini@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-03-101-112/+3
|\ \
| * | usb: create common header virtual root hub descriptorsStephen Warren2014-03-101-112/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many USB host controller drivers contain almost identical copies of the same virtual root hub descriptors. Put these into a common file to avoid duplication. Note that there were some very minor differences between the descriptors in the various files, such as: - USB 1.0 vs. USB 1.1 - Manufacturer/Device ID - Max packet size - String content I assume these aren't relevant. Cc: Thomas Lange <thomas@corelatus.se> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Gary Jennejohn <garyj@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Eric Millbrandt <emillbrandt@coldhaus.com> Cc: Pierre Aubert <p.aubert@staubli.com> Cc: Stefan Roese <sr@denx.de> Cc: Daniel Hellstrom <daniel@gaisler.com> Cc: Denis Peter <d.peter@mpl.ch> Cc: Rodolfo Giometti <giometti@linux.it> Cc: Zhang Wei <wei.zhang@freescale.com> Cc: Mateusz Zalega <m.zalega@samsung.com> Cc: Remy Bohmer <linux@bohmer.net> Cc: Markus Klotzbuecher <mk@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Gary Jennejohn <garyj@denx.de> Cc: C Nauman <cnauman@diagraph.com> Cc: David Müller <d.mueller@elsoft.ch> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Thomas Abraham <t-abraham@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Andrew Murray <amurray@embedded-bits.co.uk> Cc: Matej Frančeškin <matej.franceskin@comtrade.com> Cc: Cliff Cai <cliff.cai@analog.com> Cc: Bryan Wu <cooloney@gmail.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | | highbank: use scsi_init hookIan Campbell2014-03-101-4/+10
| | | | | | | | | | | | | | | Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Rob Herring <robh@kernel.org>
* | | m68k: Remove M5271EVB and idmr board supportMasahiro Yamada2014-03-109-810/+0
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_HZ must be always 1000, but M5271EVB.h defines it as 1000000 and idmr.h defines it as (50000000 / 64). When compiling these two boards, a warning message is displayed: time.c:14:2: warning: #warning "CONFIG_SYS_HZ must be 1000 and should not be defined by platforms" [-Wcpp] There are no board maintainers for them so this commit just deletes them. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Jason Jin <Jason.jin@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-03-0724-44/+1637
|\ \
| * | powerpc/t104xrdb: Update DDR initialization related settingsPriyanka Jain2014-03-072-28/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update following DDR related settings for T1040RDB, T1042RDB_PI -Correct number of chip selects to two as t1040 supports two Chip selects. -Update board_specific_parameters udimm structure with settings derived via calibration. -Update ddr_raw_timing sructure corresponding to DIMM. -Set ODT to off. Typically on FSL board, ODT is set to 75 ohm, but on T104xRDB, on setting this , DDR instability is observed. Board-level debugging is in progress. Verified the updated settings to be working fine with dual-ranked Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/t1040qds: Add Video - HDMI supportPriyanka Jain2014-03-074-0/+229
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040 has internal display interface unit (DIU) for driving video. T1040QDS supports video mode via -LCD using TI enconder -HDMI type interface via HDMI encoder Chrontel, CH7301C encoder which is I2C programmable is used as HDMI connector on T1040QDS. This patch add support to -enable Video interface for T1040QDS -route qixis multiplexing to enable DIU-HDMI interface on board -program DIU pixel clock gerenartor for T1040 -program HDMI encoder via I2C on board Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/t2080rdb: Add T2080PCIe-RDB board supportShengzhou Liu2014-03-0714-0/+993
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. It works in two mode: standalone mode and PCIe endpoint mode. T2080PCIe-RDB Feature Overview ------------------------------ Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz DDR Memory: - Single memory controller capable of supporting DDR3 and DDR3-LP devices - 72bit 4GB DDR3-LP SODIMM in slot Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - Two 10Gbps SFP+ ports on-board - Two 10Gbps Base-T ports on-board Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes 16 lanes configuration: - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) - SerDes-2 Lane G-H: to SATA1 & SATA2 IFC/Local Bus: - NOR: 128MB 16-bit NOR flash - NAND: 512MB 8-bit NAND flash - CPLD: for system controlling with programable header on-board eSPI: - 64MB N25Q512 SPI flash USB: - Two USB2.0 ports with internal PHY (both Type-A) PCIe: - One PCIe x4 gold-finger - One PCIe x4 connector - One PCIe x2 end-point device (C293 Crypto co-processor) SATA: - Two SATA 2.0 ports on-board SDHC: - support a TF-card on-board I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/t208xqds: fixup for t208xqdsShengzhou Liu2014-03-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Change QIXIS timing parameter CONFIG_SYS_CS3_FTIM2 to 8 from 0. Fix EMI2 for t2080qds, which was caused by adding t2081qds. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/b4860: Add workaround for errata A006384 and A006475Shaveta Leekha2014-03-071-0/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | B4860qds: Set SerDes2 refclk2 at to 156.25MHz for XFI to workShaveta Leekha2014-03-071-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change setting of SerDes2 refclk2 to have the default value as it is coming on board that is 156.25MHz, for XFI to work. Also change PLL_NUM variable to the one defined in config_mpc85xx.h for B4860 and B4420. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | 85xx/b4860: Alternate serdes protocols for B4860/B4420poonam aggrwal2014-03-072-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On B4860 and B4420, some serdes protocols can be used with LC VCO as well as Ring VCO options. Addded Alternate options with LC VCO for such protocols. For example protocol 0x2a on srds 1 becomes 0x29 if it is LC VCO. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | board/b4860qds: Add support to make PCIe SATA work on B4860QDSShaveta Leekha2014-03-071-9/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | board/b4860qds: Add support to make Aurora work on B4860QDSShaveta Leekha2014-03-072-4/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1) Add new SerDes1 protocols having Aurora in them 2) Add VSC cross point connections for Aurora to work with CPRI and SGMIIs 3) Configure VSC crossbar switch to connect SerDes1 lanes to aurora on board, by checking SerDes1 protocols 4) SerDes1 Refclks have been set properly to make Aurora, CPRI and SGMIIs to work together properly Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | powerpc: mpc8260: consolidate CONFIG_MPC8260 and CONFIG_8260Masahiro Yamada2014-03-073-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, CONFIG_MPC8260 and CONFIG_8260 were used mixed-up. All boards with mpc8260 cpu defined both of them: - CONFIG_MPC8260 was defined in board config headers and include/common.h - CONFIG_8260 was defined arch/powerpc/cpu/mpc8260/config.mk We do not need to have both of them. This commit keeps only CONFIG_MPC8260. This commit does: - Delete CONFIG_8260 and CONFIG_MPC8260 definition in config headers and include/common.h - Rename CONFIG_8260 to CONFIG_MPC8260 in arch/powerpc/cpu/mpc8260/config.mk. - Rename #ifdef CONFIG_8260 to #ifdef CONFIG_MPC8260 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
* | | kbuild, blackfin: Add CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEEDMasahiro Yamada2014-03-0724-196/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many (but not all) of Blackfin boards give -O2 option to compile under lib/ directory. That means lib/ should be speed-optimized, whereas other parts should be size-optimized. We want to keep the same behavior, but do not want to parse board/*/config.mk again and again. We've got no choice but to invent a new method. CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED, if it is enabled, gives -O2 flag only for building under lib/ directory. Dirty codes which I had marked as "FIX ME" in board/${BOARD}/config.mk have been deleted. Instead, CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED has been defined in include/configs/${BOARD}.h. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Sonic Zhang <sonic.zhang@analog.com>
* | | ppc4xx: Remove 4xx NAND booting supportStefan Roese2014-03-0711-232/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As ppc4xx currently only supports the deprecated nand_spl infrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely. This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tirumala Marri <tmarri@apm.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | | xilinx: delete meaningless .gitignore filesMasahiro Yamada2014-03-075-5/+0
|/ / | | | | | | | | | | | | | | config.tmp is never generated Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2014-03-043-19/+36
|\ \
| * | mtd: nand: omap: move omap_gpmc.h from arch/arm/include/asm to drivers/mtd/nandpekon gupta2014-03-042-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | omap_gpmc.h is a generic header used by OMAP NAND driver for all TI platfoms. Hence this file should be present in generic folder instead of architecture specific include folder. Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta <pekon@ti.com>
| * | board/ti/am335x/README: update for NAND bootpekon gupta2014-03-031-17/+36
| |/ | | | | | | | | | | | | | | | | NAND boot mode on AM335x EVM has been verified, and steps to use it has been documented and update in this README Signed-off-by: Pekon Gupta <pekon@ti.com> Acked-by: Peter Korsgaard <jacmet@sunsite.dk> Acked-by: Tom Rini <trini@ti.com>
* | arc: arcangel4: set board entry <none> to fix a build errorMasahiro Yamada2014-03-041-11/+0
| | | | | | | | | | | | | | | | There are no source files in board/synopsys/arcangel4/ directory. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
* | board: config.mk: delete unused sinclude directiveMasahiro Yamada2014-03-042-4/+0
| | | | | | | | | | | | config.tmp is not there. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | board: .gitignore: ignore board-specific generated filesMasahiro Yamada2014-03-043-0/+4
| | | | | | | | | | | | | | | | | | | | Ignore - board/cray/L1/bootscript.{c|image} - board/matrix_vision/mvblm7/bootscript.img - board/maxtir_vision/mvsmr/bootscript.img Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andre Schwarz <andre.schwarz@matrix-vision.de>
* | board: gaisler: delete unnecessary include pathMasahiro Yamada2014-03-045-10/+0
| | | | | | | | | | | | | | | | The same outputs are generated with or without -I$(TOPDIR)/board. I cannot understand why it is necessary. Remove. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Daniel Hellstrom <daniel@gaisler.com>
* | sandbox: Convert GPIOs to use driver modelSimon Glass2014-03-041-1/+6
| | | | | | | | | | | | Convert sandbox over to use driver model GPIOs. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sizes.h - consolidate for all architecturesAlexey Brodkin2014-03-0410-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Copied from Linux sources "include/linux/sizes.h" commit 413541dd66d51f791a0b169d9b9014e4f56be13c Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Tom Rini <trini@ti.com> Cc: Stefan Roese <sr@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Tom Rini <trini@ti.com> Acked-by: Stefan Roese <sr@denx.de> [trini: Add bcm Kona platforms to the patch] Signed-off-by: Tom Rini <trini@ti.com>
View Lorry Controller Status