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* treewide: mem: Move mtest related defines to KconfigWIP/2020-05-07-more-kconfig-migrationsAshok Reddy Soma2020-05-081-2/+6
| | | | | | | | | | | Move below defines which are used by mtest utility to Kconfig. CONFIG_SYS_MEMTEST_START CONFIG_SYS_MEMTEST_END Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> [trini: Fix kmcoge5ne board, re-run migration as well] Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: juno: Use PSCI based resetAndre Przywara2020-05-071-3/+1
| | | | | | | | | So far the Juno board wasn't implementing reset. Let's just use the already existing PSCI_RESET based method to avoid any extra code. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: juno: Enable OF_CONTROLAndre Przywara2020-05-072-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | The Arm Juno board was still somewhat stuck in "hardcoded land", even though there are stable DTs around, and one happens to actually be on the memory mapped NOR flash. Enable the configuration options to let the board use OF_CONTROL, and add a routine to find the address of the DTB partition in NOR flash, to use that for U-Boot's own purposes. This can also passed on via $fdtcontroladdr to any kernel or EFI application, removing the need to actually load a device tree. Since the existing "afs" command and its flash routines require flash_init() to be called before being usable, and this is done much later in the boot process, we introduce a stripped-down partition finder routine in vexpress64.c, to scan the NOR flash partitions for the DT partition. This location is then used for U-Boot to find and probe devices. The name of the partition can be configured, if needed, but defaults to "board.dtb", which is used by Linaro's firmware image provided. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini2020-05-0512-28/+676
|\ | | | | | | | | | | | | | | - Add DM model for P1010RDB - Add I2C DM Model support for P1010RDB, T1042RDB, T2080, T4240RDB, MPC8548CDS, T1024RDB, P4080, P3041DS, P2041RDB, P2020RDB, P1020RDB, P5040DS - Fix reference to READM.qe_firmware
| * powerpc: P1010RDB: Compile legacy PCIe routines conditionallyHou Zhiqiang2020-05-041-2/+2
| | | | | | | | | | | | | | | | Compile the legacy PCIe initialization reoutines for P1010RDB boards only when DM_PCI is not enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * dm: powerpc: T1040/T1042: add i2c DM supportBiwen Li2020-05-043-5/+21
| | | | | | | | | | | | | | This supports i2c DM for SoC T1040/T1042 Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * dm: powerpc: T2080/T2081: add i2c DM supportBiwen Li2020-05-041-3/+16
| | | | | | | | | | | | | | This supports i2c DM for SoC T2080/T2081 Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * dm: ppc: T4240: add i2c DM supportBiwen Li2020-05-042-8/+295
| | | | | | | | | | | | | | This supports i2c DM for SoC T4240 Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * dm: ppc: MPC8548CDS: add i2c DM supportBiwen Li2020-05-041-1/+2
| | | | | | | | | | | | | | This supports i2c DM for board MPC8548CDS Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * dm: ppc: p1010: add i2c DM supportBiwen Li2020-05-041-1/+155
| | | | | | | | | | | | | | This supports i2c DM for SoC P1010 Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * dm: powerpc: T1023/T1024: add i2c DM supportBiwen Li2020-05-043-7/+162
| | | | | | | | | | | | | | This supports i2c DM for SoC T1023/T1024 Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * dm: powerpc: P1020: add i2c DM supportBiwen Li2020-05-041-1/+23
| | | | | | | | | | | | | | This supports i2c DM for SoC P1020 Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86WIP/04May2020Tom Rini2020-05-041-0/+7
|\ \ | | | | | | | | | - Support 64-bit U-Boot as the payload for coreboot x86
| * | x86: Add a 64-bit 'coreboot64' buildSimon Glass2020-05-041-0/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Coreboot is a first-stage bootloader mostly used on x86 devices as an alternative to UEFI. Coreboot runs in 32-bit mode. U-Boot currently supports booting from coreboot as a second-stage bootloader, also in 32-bit mode. However it is useful to be able to run U-Boot in 64-bit mode. To do this we can have a 32-bit SPL which switches over the CPU and jumps to a 64-bit U-Boot proper. Add a new 'coreboot64' board for running 64-bit U-Boot from coreboot. This uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot. This allows running 64-bit EFI images on x86, for example, without needing a native U-Boot port for a board. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge tag 'u-boot-imx-20200502' of ↵Tom Rini2020-05-0417-65/+2222
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX for 2020.07 ---------------- - imxrt: fix LCD clock, fix doc - new board: Coral Dev - imx8: enable Cache in SPL. SNVS, update SCFW API - imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading - MX6ULL : is_imx6ull to include i.MX6ULZ - Net: add config to enable TXC delay Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914
| * | imxrt1020-evk: README: change dd command destinationGiulio Benetti2020-05-011-2/+2
| | | | | | | | | | | | | | | | | | | | | Set dd "of=" to "of=/dev/sdX" to be generic and prevent host hard drive damage. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | imxrt1050-evk: README: change dd command destinationGiulio Benetti2020-05-011-2/+2
| | | | | | | | | | | | | | | | | | | | | Set dd "of=" to "of=/dev/sdX" to be generic and prevent host hard drive damage. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | arm: imx: Add support for Google's Coral Dev BoardAlifer Moraes2020-05-017-0/+2079
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for Google's Coral Dev Board based on i.MX8MQ. https://coral.ai/products/dev-board The Phanbell naming has been used here to match the naming convention used in Google's U-Boot source tree: https://coral.googlesource.com/uboot-imx/ Co-developed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com> Tested-by: Marco Franchi <marcofrk@gmail.com>
| * | board: apalis_imx6: Add KSZ9131 phy skew settingsPhilippe Schenker2020-05-011-16/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds skew register settings for KSZ9131. It checks first which phy is on the board and then applies the correct skew settings. Skew settings calculation for the KSZ9131: The i.MX6 SoC has an output skew tolerance of -100ps to 900ps. All PCB traces where routed exactly the same length so we can calculate the skew settings without taking the length into consideration. The traces are all length matched. RXC skew (PHY to MAC): - We use the 2ns DLL controlled delay on the PHY - We do not use the skew registers This results in the following values: RXC PHY fixed Delay 2000ps PHY Added Delay 0ps T_setup_R min 2.00ns T_setup_R typ 2.00ns T_setup_R max 2.00ns T_hold_R min 1.60ns T_hold_R typ 2.00ns T_hold_R max 2.40ns That means we are well within RGMII specs. TXC skew (MAC to PHY): - We use the 2ns DLL controlled delay on the PHY - We then subtract ~0.6ns with TXD[0:3] and TXC clock pad skew register in a resulting ~1.4ns delay. This results in the following values under consideration of the tolerances: TXC min TXC typ TXC max MAC min -100ps -100ps -100ps MAC max 900ps 900ps 900ps PHY fixed Delay 2000ps 2000ps 2000ps PHY added Delay -340ps -600ps -859ps T_setup_T min 1.56ns 1.30ns 1.04ns T_setup_T typ 2.06ns 1.80ns 1.54ns T_setup_T max 2.56ns 2.30ns 2.04ns T_hold_T min 1.04ns 1.30ns 1.56ns T_hold_T typ 1.94ns 2.20ns 2.46ns T_hold_T max 2.84ns 3.10ns 3.36ns This shows that T_hold_T min and T_setup_T min times are out of spec for RGMII timing. However the KSZ9131 has a minimal value for this time of 0.8ns which is met under all circumstances. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
| * | board: verdin-imx8mm: Add KSZ9131 phy skew settingsPhilippe Schenker2020-05-011-23/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch determines which phy is placed on the board with the PHY ID then it sets the same settings for KSZ9031 as before but for KSZ9131 it enables both RXC and TXC delay lines in the PHY. This will compensate the missing delay from the MAC. Other skew settings are not needed as the traces on board are routed exactly the same length Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Tested-by: Igor Opaniuk <igor.opaniuk@toradex.com> Acked-by: Igor Opaniuk <igor.opaniuk@toradex.com>
| * | verdin-imx8mm: Change board phy skew values for our ksz9031Philippe Schenker2020-05-011-8/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patches uses the existing functions for interacting with the KSZ9031 and uses the values appropriate for our board. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Tested-by: Igor Opaniuk <igor.opaniuk@toradex.com> Acked-by: Igor Opaniuk <igor.opaniuk@toradex.com>
| * | mx8mq_evk: Remove unrelated commentFabio Estevam2020-05-011-1/+0
| | | | | | | | | | | | | | | | | | | | | The comment does not relate to the setup_i2c() function, so just remove it. Signed-off-by: Fabio Estevam <festevam@gmail.com>
| * | imx8mp_evk: Remove unrelated commentFabio Estevam2020-05-011-1/+0
| | | | | | | | | | | | | | | | | | | | | The comment does not relate to the setup_i2c() function, so just remove it. Signed-off-by: Fabio Estevam <festevam@gmail.com>
| * | imx: imx8m*: Remove do_reset from board filesClaudius Heine2020-05-014-36/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the `do_reset` implementation of `arch/arm/lib/reset.c` in SPL instead. It is very close to what is done here, anyway, and plays more nicely with the rest of U-Boot than adding a custom `do_reset` implementation into board files. `do_reset` from `arch/arm/lib/reset.c` calls `reset_cpu` with 0 as the addr parameter while the boards are passing WDOG1_BASE_ADDR. This is ok because the `reset_cpu` implementation uses WDOG1_BASE_ADDR by default if 0 is passed in. Co-Authored-by: Harald Seiler <hws@denx.de> Signed-off-by: Claudius Heine <ch@denx.de> Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
| * | imx8: Configure SNVSFranck LENORMAND2020-05-011-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a module to configure the tamper and secure violation of the SNVS using the SCU API. The module also adds some commands: - snvs_cfg: Configure the SNVS HP and LP registers - snvs_dgo_cfg: Configure the SNVS DGO bloc if present (8QXP) - tamper_pin_cfg: Change the configuration of the tamper pins - snvs_clear_status: Allow to write to LPSR and LPTDSR to clear status bits Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | | Merge tag 'u-boot-rockchip-20200501' of ↵Tom Rini2020-05-044-15/+17
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - dts clean up to use -u-boot for px30, rk3399 boards - dts sycn from upstream kernel for rk3328, rk3399 - add rockchip rng driver - new board support: rk3328-roc-cc, rk3399-roc-pc,Nanopi M4 2GB
| * | rockchip: rk3399: Add Nanopi M4 2GB board supportDeepak Das2020-05-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | commit b2f5da9dd068 ("rockchip: rk3399: Add Nanopi M4 board support") added support for Nanopi M4 board with Dual-Channel 4GB LPDDR3-1866 RAM. This patch adds another variant of NanoPi M4 board with Dual-Channel 2GB DDR3-1866 RAM. Signed-off-by: Deepak Das <deepakdas.linux@gmail.com>
| * | rk3399: Add ROC-RK3399-PC Mezzanine boardSuniel Mahesh2020-05-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Firefly ROC-RK3399-PC Mezzanine board which is an extension board on top of roc-rk3399-pc. Will drop the separate defconfig file, once we support the board detection at runtime. Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk3328: Add support for ROC-RK3328-CC boardChen-Yu Tsai2020-05-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit card size development board based on the Rockchip RK3328 SoC, with: - 1/2/4 GB DDR4 DRAM - eMMC connector for optional module - micro SD card slot - 1 x USB 3.0 host port - 2 x USB 2.0 host port - 1 x USB 2.0 OTG port - HDMI video output - TRRS connector with audio and composite video output - gigabit Ethernet - consumer IR receiver - debug UART pins The ROC-RK3328-CC has the enable pin of the SD card power switch tied to GPIO_0_D6. This pin also has the function SDMMC0_PWREN, which is muxed by default. SDMMC0_PWREN is an active high signal controlled by the MMC controller, however the switch enable is active low, and pulled low (enabled) by default to make things work on boot. As such, we need to mux away from SDMMC0_PWREN and use GPIO to enable power to the card. The default GPIO state for the pin is pull-down and input, which doesn't require extra configuration when paired with the external pull-down and active low switch. Deal with this by enabling regulator support in SPL, and setting "u-boot,dm-spl" for the regulator and other device nodes needed for muxing the pin. The device tree file is synced from the Linux kernel next-20200324. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: board: roc-pc-rk3399: Remove support for push buttonSuniel Mahesh2020-04-291-15/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of a power interruption, human intervention is required which is not desirable if the device is installed at a remote location. Drop yellow LED as it is not much of use. Keep red LED(diy-led) as it is, to indicate board in full power mode. Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spiWIP/30Apr2020Tom Rini2020-04-301-0/+3
|\ \ \ | |_|/ |/| | | | | | | | - distro boot support for SPI flash - sifive spi flash driver
| * | sifive: fu540: Enable spi-nor flash supportJagan Teki2020-04-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HiFive Unleashed A00 support is25wp256 spi-nor flash, So enable the same and add test result log for future reference. Tested on SiFive FU540 board. Thanks to Sagar for various use cases and tests. [QUAD mode in dt with spi-tx-bus-width: <4>] pp opcode = 0x34 [QUAD MODE] read opcode = 0x6c [QUAD MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc [SPI MODE in dt with spi-tx-bus-width: <1>] pp opcode = 0x12 [SPI MODE] read opcode = 0xc [SPI MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
* | | Merge tag 'xilinx-for-v2020.07-rc2' of ↵Tom Rini2020-04-308-38/+72
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2020.07-rc2 mmc: - Fix dt property handling via generic function clk: - Fix versal watchdog clock setting nand: - Fix zynq nand command comparison xilinx: - Enable ubifs - Sync board_late_init configurations with initrd_high setup - Make custom distro boot more verbose zynq: - Kconfig alignments - Fix nand cse configuration zynqmp: - Fix zcu104 low level qspi configuration - Small DT updates Signed-off-by: Tom Rini <trini@konsulko.com>
| * | | xilinx: Move bootmode detection to separate functionMichal Simek2020-04-272-16/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create special function for reading bootmode on Versal and ZynqMP. Zynq is using specific function (without mask) already. Future patches will be calling this function from different location too. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | xilinx: Move initrd_high setup to common locationMichal Simek2020-04-273-12/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Moving to common location initrd_high is also setup for Zynq which hasn't done in run time code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | xilinx: zynqmp: Fix MIO 18 configuration on zcu104 revCMichal Simek2020-04-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Without this change QSPI is not detected on zcu104 revC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | xilinx: Introduce board_late_init_xilinx()Michal Simek2020-04-277-9/+28
| | |/ | |/| | | | | | | | | | | | | | | | This function should keep common shared late configurations for Xilinx SoCs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2020-04-3012-26/+60
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb, ls1043ardb, lx2160ardb, ls2088ardb, ls1088ardb. - Add GICv3 support for ls1028a, ls2088a, ls1088a. - Add lpuart support on ls1028aqds. - Few bug fixes and updates on ls2088a, ls1012a, ls1046a, ls1021a based platforms.
| * | | driver: net: fm: add DM ETH supportMadalin Bucur2020-04-294-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | configs: ls1028aqds: add lpuart configYuantian Tang2020-04-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add lpuart config to enable lpuart feature. Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Yuantian Tang <andy.tang@nxp.com>. Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | board: freescale: ls1028a: mux changes for lpuartYuantian Tang2020-04-291-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mux changes in board file to enable lpuart1 and macro define for lpuart1 used for mux changes in board configuation register 13 Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | board: ls2088ardb: transition to DM_ETHIoana Ciornei2020-04-292-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2 Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH is activated. Also, force the PCI devices to be enumerated at probe time. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | board: ls1088ardb: transition to DM_ETHIoana Ciornei2020-04-292-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2 Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH is activated. Also, force the PCI devices to be enumerated at probe time. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | fsl-layerscape: Move GIC RD tables init to soc.cHou Zhiqiang2020-04-281-30/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move GIC redistributor tables initialization to CPU setup function. This patch introduces a GIC redistributor tables init function, and moves the function of reserving memory for GIC redistributor tables to soc.c and adds a argument for the memory size to reserve, BTW rename the function so that it is more readable. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | board: lx2160a: Align RD tables address to 64KBHou Zhiqiang2020-04-281-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the lower 16bit of the redistributor pending table is reserved for describing the memory attributes, we must give a 64KB aligned address to the GIC LPI initialization function. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | board: lx2160a: Add check in GIC RD tables initHou Zhiqiang2020-04-281-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Program the GIC redistributor tables only when succeeded to reserve memory for them, otherwise kernel will lose the chance to program them using allocated memory. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | armv8: ls1046ardb: update the DIMM WRLVL_START valueYuantian Tang2020-04-281-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | The WRLVL_START values are optimized for old DDR MTA18ASF1G72AZ. Update DDR struct to set new WRLVL_START values so that the new DIMM MTA18ADF2G72AZ get optimized and the old DIMM still works. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shWIP/29Apr2020Tom Rini2020-04-294-11/+7
|\ \ \ | |_|/ |/| | | | | - rmobile gen2/gen3 DTS sync and defconfig consolidation
| * | ARM: dts: rmobile: Synchronize Gen3 DTs with Linux 5.6.2Marek Vasut2020-04-282-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Synchronize R-Car Gen3 device trees with Linux 5.6.2, commit 9fbe5c87eaa9b72db08425c52c373eb5f6537a0a . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | ARM: rmobile: Unify Gen3 Salvator-X(S) and ULCB defconfigsMarek Vasut2020-04-282-6/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | The r8a779{5,6,65}_salvator-x and r8a779{5,6,65}_ulcb_defconfig were building the same target, except for the default DT. The default DT is however only a detail, as the actual DT to be used to configure U-Boot is detected automatically based on the CPU ID, hence the default DT is not meaningful. Unify each three defconfigs per board to reduce the duplication. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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