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* lib: merge CRC16-CCITT into u-boot/crc.hPhilipp Tomsich2018-12-083-3/+3
| | | | | | | | | This merges the CRC16-CCITT headers into u-boot/crc.h to prepare for rolling CRC16 into the hash infrastructure. Given that CRC8, CRC32 and CRC32-C already have their prototypes in a single header file, it seems a good idea to also include CRC16-CCITT in the same. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2018-12-072-14/+29
|\ | | | | | | | | - Various axp209 fixes - Fixes for OLinuXino-A20-Lime2 / OLinuXino-A20-Lime2-eMMC
| * sunxi: update README.sunxi64Andre Przywara2018-12-071-6/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the Allwinner port in the official mainline ARM Trusted Firmware repository has reached feature parity with the "legacy" ATF port, let's use the opportunity to update the Allwinner 64-bit build instructions. This changes: - Update ATF build instructions to use the mainline repo. - Add quick command lines for TL;DR people. - Mention Allwinner H6 build target. - Mention pre-built FEL binaries. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: board: Print error after power initialization failsOlliver Schinagl2018-12-071-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently during init, we enable all power, then enable the dram and after that check whether there was an error during power-up. This makes little sense, we should enable power and then check if power was brought up properly before we continue to initialize other things. This patch moves the DRAM init after the power failure check. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Signed-off-by: Priit Laes <plaes@plaes.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
* | board: ti: ks2_evm: Over ride spl_get_load_buffer functionKeerthy2018-12-061-0/+5
|/ | | | | | | | | | | | | | | | Currently k2 spi boot is broken as the image header is getting copied to an invalid memory location CONFIG_SYS_TEXT_BASE - sizeof (struct image_size) which maps to 0xc000000 - 0x40 = 0xbffffc0 being a reserved location. We cannot change the CONFIG_SYS_TEXT_BASE address as the single stage boots like UART boot will need the address to be 0xc000000 hence override the spl_get_load_buffer to have image_header address as CONFIG_SYS_TEXT_BASE aka 0xc000000 Signed-off-by: Keerthy <j-keerthy@ti.com>
* rockchip: rk3399: Add MAINTAINERS entryTom Rini2018-12-061-0/+5
| | | | | | | Add an entry for the Ficus EE board to the existing rock960 MAINTAINERS file. Signed-off-by: Tom Rini <trini@konsulko.com>
* rockchip: rk3399: Add common Rock960 family from VamrsManivannan Sadhasivam2018-12-065-0/+229
| | | | | | | | | | | | | | | | | | | | | | | | Rock960 is a family of boards based on Rockchip RK3399 SoC from Vamrs. It consists of Rock960 (Consumer Edition) and Ficus (Enterprise Edition) 96Boards. Below are some of the key differences between both Rock960 and Ficus boards: 1. Different host enable GPIO for USB 2. Different power and reset GPIO for PCI-E 3. No Ethernet port on Rock960 The common board support will be utilized by both boards. The device tree has been organized in such a way that only the properties which differ between both boards are placed in the board specific dts and the reset of the nodes are placed in common dtsi file. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> [Added instructions for SD card boot] Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Peter Robinson <pbrobinson@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2018-12-052-2/+2
|\ | | | | | | | | | | | | | | - Various MTD fixes from Boris - Zap various unused / legacy paths. - pxa3xx NAND update from Miquel Signed-off-by: Tom Rini <trini@konsulko.com>
| * spi: Zap CONFIG_HARD_SPIJagan Teki2018-11-272-2/+2
| | | | | | | | | | | | | | | | | | | | In legacy CONFIG_HARD_SPI initalizing spi_init code, which was removed during dm conversion cleanup. So remove the dead instances of CONFIG_HARD_SPI, and related code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* | riscv: ax25-ae350: Pass dtb address to u-boot with a1 registerRick Chen2018-12-051-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ax25-ae350 use CONFIG_OF_BOARD via a2 and CONFIG_SYS_SDRAM_BASE to boot from ram which allow the board to override the fdt address originally. But after this patch riscv: save hart ID and device tree passed by prior boot stage It provide prior_stage_fdt_address which offer a temporary memory address to keep the dtb address passing from loader(gdb) to u-boot with a1. So passing via a2 and CONFIG_SYS_SDRAM_BASE is redundant and can be removed. And it also somehow may corrupted BBL if it was be arranged in CONFIG_SYS_SDRAM_BASE. In board_fdt_blob_setup() When boting from ram: prior_stage_fdt_address will be use to reserved dtb temporarily. When booting from ROM: dtb will be pre-burned in CONFIG_SYS_FDT_BASE, if it is flash base. Or CONFIG_SYS_FDT_BASE maybe a memory map space (NOT RAM or ROM) which is provided by HW. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
* | riscv: Add S-mode defconfigs for QEMU virt machineAnup Patel2018-12-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | This patch adds S-mode defconfigs for QEMU virt machine so that we can run u-boot in S-mode on QEMU using M-mode runtime firmware (BBL or equivalent). Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* | riscv: qemu: Use different SYS_TEXT_BASE for S-modeAnup Patel2018-12-051-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When u-boot runs in S-mode, the M-mode runtime firmware (BBL or equivalent) uses memory range in 0x80000000 to 0x80200000. Due to this, we cannot use 0x80000000 as SYS_TEXT_BASE when running in S-mode. Instead for S-mode, we use 0x80200000 as SYS_TEXT_BASE. Even Linux RISC-V kernel ignores/reserves memory range 0x80000000 to 0x80200000 because it runs in S-mode. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* | ARM: dts: Turn ULCB into Multi-DTB configMarek Vasut2018-12-041-0/+18
| | | | | | | | | | | | | | | | Bundle DTBs for R8A7795, R8A7796 ULCB variants into single U-Boot build and let U-Boot choose between them based on the CPU model. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | ARM: dts: Turn Salvator-X into Multi-DTB configMarek Vasut2018-12-041-0/+22
| | | | | | | | | | | | | | | | | | Bundle DTBs for R8A7795, R8A7796, R8A77965 Salvator-X variants into the single U-Boot build and let U-Boot choose between them based on the CPU model. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | ARM: rmobile: Drop unused macros from Gen3 boardsMarek Vasut2018-12-042-3/+0
| | | | | | | | | | | | | | | | Drop unused MSTP macros from Gen3 boards. These are no longer needed as the boards are using clock framework to manipulate clock. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | MAINTAINERS: board: qcom: db820c: update email.Jorge Ramirez-Ortiz2018-12-031-1/+1
| | | | | | | | | | | | Update email address Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
* | Merge tag 'xilinx-for-v2019.01' of git://git.denx.de/u-boot-microblazeTom Rini2018-12-039-35/+52
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx changes for v2019.01 microblaze: - Use default functions for memory decoding - Showing model from DT zynq: - Fix spi flash DTs - Fix zynq_help_text with CONFIG_SYS_LONGHELP - Tune cse/mini configurations - Enabling cse/mini testing with current targets zynqmp: - Enable gzip SPL support - Fix chip detection logic - Tune mini configurations - DT fixes(spi-flash, models, clocks, etc) - Add support for OF_SEPARATE configurations - Enabling mini testing with current targets - Add mini mtest configuration - Some minor config setting nand: - arasan: Add subpage configuration net: - gem: Add 64bit DMA support
| * | arm64: zynqmp: Wire mini-emmc1 configuration with zcu102Michal Simek2018-11-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For testing purpose use zcu102 which has SD at controller 1 and this can be used for testing this mini configuration. U-Boot 2018.11-00279-gdc482e7ee092 (Nov 30 2018 - 10:22:56 +0100) Model: ZynqMP MINI EMMC1 Board: Xilinx ZynqMP DRAM: 512 MiB EL Level: EL3 MMC: sdhci@ff170000: 0 In: dcc Out: dcc Err: dcc ZynqMP> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Wire mini-emmc0 configuration with zcu100Michal Simek2018-11-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For testing purpose use zcu100 which has SD at controller 0 and this can be used for testing this mini configuration. U-Boot 2018.11-00281-gc5d48466e76e (Nov 30 2018 - 10:41:05 +0100) Model: ZynqMP MINI EMMC0 Board: Xilinx ZynqMP DRAM: 512 MiB EL Level: EL3 MMC: sdhci@ff160000: 0 In: dcc Out: dcc Err: dcc ZynqMP> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Start usb ethernet gadget automaticallyMichal Simek2018-11-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | If only usb ethernet gadget is enabled it can start automatically. If more gagdets are enabled usb ethernet gadget can be bind by "bind /amba/usb1@ff9e0000/dwc3@fe300000 usb_ether" (on zcu100) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Add mini mtest configurationMichal Simek2018-11-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This configuration is useful when you want to run small u-boot and perform DDR memory test to make sure that DDR is properly configured. It is use for board bringup because alternative u-boot memory tests is quite good. Configuration is running out of OCM. As is done for others mini configurations 0x80 bytes for variables is enough and only default variables are stored there. Alternative memtest is enabled and also 2GB of DDR via DTS files. Configuration is enabling ZYNQMP_PSU_INIT_ENABLED and include psu_init() from zcu102 for testing purpose. In case of size issue this can be moved to SPL configuration as is done for mini_qspi configuration but it is not a problem now. Log: U-Boot 2018.11-00268-gbd58b8ba8915 (Nov 29 2018 - 15:33:35 +0100) Model: ZynqMP MINI Board: Xilinx ZynqMP DRAM: WARNING: Initializing TCM overwrites TCM content 2 GiB EL Level: EL3 In: dcc Out: dcc Err: dcc ZynqMP> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Enable SPL for mini qspi configurationMichal Simek2018-11-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Wire up mini_qspi SPL with zcu102 for testing purpose. Normally mini u-boot runs with FSBL/SPL for certain board. Enabling SPL and configuration from zcu102 helps with testing. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Wire SPL configuration for cse nor/nand targetsMichal Simek2018-11-292-0/+2
| | | | | | | | | | | | | | | | | | | | | These symlinks are here only for testing purpose where SPL is used for soc configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | microblaze: Use standard functions for memory decodingMichal Simek2018-11-261-24/+3
| | | | | | | | | | | | | | | | | | The standard function is less error prone than custom one. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Guard zynq_help_text with CONFIG_SYS_LONGHELPMichal Simek2018-11-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If SYS_LONGHELP is disabled the following warning is generated: board/xilinx/zynq/cmds.c:496:13: warning: ‘zynq_help_text’ defined but not used [-Wunused-variable] Normal way for fixing this is to guard the whole variable. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Fix logic in CG/EG/EV detectionSiva Durga Prasad Paladugu2018-11-261-11/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VCU disable bit(8) in IP disable register of efuse is valid only if PL powered up and hence PL powerup status has to be considered while determining the CG part also. This patch considers the PL powerup status and ignores the VCU disable bit if PL not powered up. This fixes the issue of "unknown" id for CG parts if PL not powered up and VCU bit(8) is not set. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge tag 'signed-rpi-next' of git://github.com/agraf/u-bootTom Rini2018-12-031-8/+6
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch queue for rpi - 2018-12-03 A few Raspberry Pi specific changes this time: - Allow 2nd MMC device - Support RPi 3 Model A+ - Allow UUID to find filesystem
| * | | rpi: add 3 Model A+Jonathan Gray2018-12-031-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Raspberry Pi 3 Model A+ to list of models, the revision code is 0xE according to the list on raspberrypi.org. Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | | rpi: add URL of official revision code listJonathan Gray2018-12-031-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace various third party lists of Raspberry Pi revision codes in a comment with the list on raspberrypi.org. Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* | | | board: MCR3000: use new DM watchdogChristophe Leroy2018-12-032-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch switches MCR3000 board to the new DM watchdog. The change in u-boot.lds is because MCR3000.o grows a bit with this patch and doesn't fit anymore below env_offset on some versions of GCC. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
* | | | board: MCR3000: Activate CONFIG_DM and CONFIG_OF_CONTROLChristophe Leroy2018-12-031-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Add mcr3000 device tree and activate CONFIG_DM and CONFIG_OF_CONTROL Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
* | | | arm: baltos: remove unused headerYegor Yefremov2018-12-031-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OnRISC Baltos series uses SoM with tps65910 PMIC, so remove "power/tps65217.h" header inclusion. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | arm: baltos: move the board to CONFIG_BLKYegor Yefremov2018-12-032-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use DM for both MMC and USB subsystems and use dedicated DTS for U-Boot configuration. Disable SPL support for GPIO and remove EVMSK leftover for DDR power control via GPIO. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | arc: devboards: Implement checkboard()Alexey Brodkin2018-12-033-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | This allows us to print nice board name on boot. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | | | arc: emsdp: Refactor register and bit accessesAlexey Brodkin2018-12-031-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of "base + offset" define all registers right away and access them later via direct defines. Generate bit masks with "BIT" macro. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | | | arc: emsdp: Read real CPU clock value from hardwareAlexey Brodkin2018-12-031-3/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We do real CPU clock measurement with help of built-in counters. Thus we may accommodate different real clock values that appear in different FPA images instead of relying on something hard-coded in the .dtb. And while at it make make SDIO base address define look similar to others with casting to "(void *)". Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | | | arc: Get rid of board-specific print_cpuinfo()Alexey Brodkin2018-12-032-18/+0
|/ / / | | | | | | | | | | | | | | | | | | | | | Since we now do advanced CPU identification in generic ARC code there's no need to have per-board hardcoded data. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | | Merge tag 'pull-30nov18' of git://git.denx.de/u-boot-dmTom Rini2018-11-306-83/+143
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix sound on sandbox Convert TPM fully to DM Tidy up sandbox I2C emulation Add a 'make qcheck' target for faster testing A few other misc things (dropped the final patch which breaks clang for some reason)
| * | | tpm: Convert to use a device parameterSimon Glass2018-11-296-83/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present many TPM calls assume there is only one TPM in the system and look up this TPM themselves. This is inconsistent with driver model, which expects all driver methods to have a device parameter. Update the code to correct this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | mips: mt76xx: gardena-smart-gateway: Add factory data variable handlingStefan Roese2018-11-301-0/+269
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some factory data is stored in the SPI NOR and needs to get extracted from there into U-Boot environment variables. This patch also includes a board-specific command "fd_write" to provide some dummy / default values for this factory-data in the SPI NOR flash. This should only be necessary for testing purposes though. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | | Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogicTom Rini2018-11-2932-318/+253
|\ \ \ \ | |/ / / |/| | | | | | | | | | | | | | | | | | | Cleanup and update towards support for Amlogic Meson AXG SoCs : - mmc: meson-gx: Add AXG compatible - net: designware: add meson meson compatibles - Amlogic Meson cleanup for AXG SoC support
| * | | ARM: meson: factorize common code out amlogic's boardsJerome Brunet2018-11-264-48/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now we have moved all the Amlogic board support to common generic board code, we can move the identical board_init() and ft_board_setup() functions to weak functions into the board-common mach-meson file. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | | board: amlogic: add support for S400 boardNeil Armstrong2018-11-264-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The S400 board is the Amlogic AXG SoC reference board including : - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz - 1GB DDR4 SDRAM - 10/100 Ethernet - 2 x USB 2.0 Host - eMMC - Infrared receiver - SDIO WiFi Module - MIPI DSI Connector - Audio HAT Connector - PCI-E M.2 Connectors Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | | ARM: meson: rework soc arch file to prepare for new SoCJerome Brunet2018-11-263-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We are about to add support for the Amlogic AXG SoC. While very close to the Gx SoC family, we will need to handle a few thing which are different in this SoC. Rework the meson arch directory to prepare for this. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | | ARM: rework amlogic configurationJerome Brunet2018-11-263-36/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rework the board SYS_BOARD, SYS_VENDOR and SYS_CONFIG_NAME setup by moving the board Kconfig into the mach-meson Kconfig to make it easier to add new boards for a SoC architecture and add a custom config header or custom board handler for a platform. This drops the board CONFIGs and the duplicate boards configs headers in favor of a single meson64.h config header. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | | board: amlogic: factorise gxbb boardsJerome Brunet2018-11-267-80/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The nanopi-k2 and the odroid-c2 are similar enough to be supported by the same u-boot board. This change use odroid-c2 u-boot board for the nanopi-k2 as well. Dedicated defconfig are kept to customize the names and device tree. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | | board: amlogic: move khadas-vim2 as q200 ref boardNeil Armstrong2018-11-266-7/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Khadas vim2 derive from amlogic s912 reference design (Q200). This patch moves the khadas-vim2 board support to a generic Q200 board, while keeping a dedicated defconfig to customize the names and device tree. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | | board: amlogic: remove p212 derivativesJerome Brunet2018-11-2611-162/+0
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Khadas vim and the libretech aml-s905x-cc (aka Potato) derive from amlogic s905x reference design (P212). All the code in these board is a copy/paste from the p212, which is tedious to maintain. This change use p212 u-boot board for all these boards, while keeping a dedicated defconfig to customize the names and device tree. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | | arm: MediaTek: add basic support for MT7623 boardsWeijie Gao2018-11-284-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a general board file based on MT7623 SoCs from MediaTek. As this u-boot is loaded by MTK proprietary preloader, there is no low level initializtion codes. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | arm: MediaTek: add basic support for MT7629 boardsRyder Lee2018-11-284-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a general board file based on MT7629 SoCs from MediaTek. Apart from the generic parts (cpu) we add some low level init codes and initialize the early clocks. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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