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* configs: fu540: enable gpio driverSagar Shrikant Kadam2019-10-181-0/+3
| | | | | | | | Enable the DM based GPIO driver for FU540-C000 SoC. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: sifive: fu540: set serial environment variable from otpSagar Shrikant Kadam2019-09-031-4/+14
| | | | | | | | | | This patch sets the serial# environment variable by reading the board serial number from the OTP memory region. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: sifive: fu540: Enable SiFive SPI and MMC SPI driversBhargav Shah2019-07-191-0/+6
| | | | | | | | | | | This patch enables SiFive SPI and MMC SPI drivers for the SiFive Unleashed board. Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* riscv: sifive: fu540: Setup ethaddr env variable using OTPAnup Patel2019-07-191-0/+122
| | | | | | | | This patch extends SiFive FU540 board support to setup ethaddr env variable based on board serialnum read from OTP. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* clk: sifive: Drop GEMGXL clock driverAnup Patel2019-07-191-1/+0
| | | | | | | | | | The GEMGXL clock driver is now directly part of Cadence MACB ethernet driver in upstream Linux kernel. There is no separate GEMGXL clock driver in upstream Linux kernel hence we drop GEMGXL clock driver from U-Boot as well. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: sifive: fu540: Enable GEMGXL MGMT driverBin Meng2019-06-011-0/+1
| | | | | | | | Enable the new GEMGXL MGMT driver so that GEM 10/100 Mbps works now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: fu540: enable SMPLukas Auer2019-04-081-0/+1
| | | | | | Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: Add SiFive FU540 board supportAnup Patel2019-02-274-0/+73
This patch adds SiFive FU540 board support. For now, only SiFive serial, SiFive PRCI, and Cadance MACB drivers are only enabled. The SiFive FU540 defconfig by default builds U-Boot for S-Mode because U-Boot on SiFive FU540 will run in S-Mode as payload of BBL or OpenSBI. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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