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* Revert "riscv: sifive: fu540: Add gpio-restart support"WIP/06Jul2020Tom Rini2020-07-061-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | As part of merging the next branch in to master, the sifive_fu540 will fail to link: riscv64-linux-ld.bfd: lib/built-in.o: in function `panic_finish': lib/panic.c:28: undefined reference to `do_reset' make[2]: *** [spl/u-boot-spl] Error 1 make[1]: *** [spl/u-boot-spl] Error 2 make: *** [sub-make] Error 2 And while the "fix the build" option of enabling CONFIG_SPL_SYSRESET may solve the issue, it is unclear that it is the correct path exactly. For the moment, I am reverting this commit and take a "revert the revert" and proper fix as soon as it's available. This reverts commit cdae446461191714d692190da1ad4344398adc57. Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Anup Patel <anup.patel@wdc.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Bin Meng <bin.meng@windriver.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* riscv: sifive: fu540: Add gpio-restart supportBin Meng2020-07-031-0/+2
| | | | | | | | | | The HiFive Unleashed board wires GPIO pin#10 to the input of the system reset signal. This adds gpio reboot support. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
* sifive: fu540: Add sample SD gpt partition layoutJagan Teki2020-06-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a sample GPT partition layout for SD card, right now three important partitions are added to make the system bootable. partition layout: Part Start LBA End LBA Name Attributes Type GUID Partition GUID 1 0x00000022 0x00000821 "loader1" attrs: 0x0000000000000000 type: 5b193300-fc78-40cd-8002-e86c45580b47 guid: cbcbef44-e627-42bc-b134-93b6f3784b8c 2 0x00000822 0x00002821 "loader2" attrs: 0x0000000000000000 type: 2e54b353-1271-4842-806f-e436d6af6985 guid: f54eba28-d8de-4852-978d-1a673777e2ae 3 0x00002822 0x00020821 "rootfs" attrs: 0x0000000000000004 type: 0fc63daf-8483-4772-8e79-3d69d8477de4 type: linux guid: 9561df46-8d55-4799-a83b-cfee9ef6ff93 Note: - loader1 would be fsbl or spl - loader2 would be U-Boot or U-Boot proper Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
* riscv: sifive: fu540: add SPL configurationPragnesh Patel2020-06-041-1/+9
| | | | | | | | | | | | | | | Add a support for SPL which will boot from L2 LIM (0x0800_0000) and then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin) from MMC boot devices. SPL related code is leveraged from FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* riscv: cpu: fu540: Add support for cpu fu540Pragnesh Patel2020-06-041-1/+1
| | | | | | | | | | Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* sifive: fu540: add ddr driverPragnesh Patel2020-06-041-0/+2
| | | | | | | | | Add driver for fu540 to support ddr initialization in SPL. This driver is based on FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: sifive: fu540: Use OTP DM driver for serial environment variablePragnesh Patel2020-06-041-0/+2
| | | | | | | | | | Use the OTP DM driver to set the serial environment variable. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* sifive: fu540: Enable spi-nor flash supportJagan Teki2020-04-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HiFive Unleashed A00 support is25wp256 spi-nor flash, So enable the same and add test result log for future reference. Tested on SiFive FU540 board. Thanks to Sagar for various use cases and tests. [QUAD mode in dt with spi-tx-bus-width: <4>] pp opcode = 0x34 [QUAD MODE] read opcode = 0x6c [QUAD MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc [SPI MODE in dt with spi-tx-bus-width: <1>] pp opcode = 0x12 [SPI MODE] read opcode = 0xc [SPI MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
* configs: fu540: enable gpio driverSagar Shrikant Kadam2019-10-181-0/+3
| | | | | | | | Enable the DM based GPIO driver for FU540-C000 SoC. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: sifive: fu540: Enable SiFive SPI and MMC SPI driversBhargav Shah2019-07-191-0/+6
| | | | | | | | | | | This patch enables SiFive SPI and MMC SPI drivers for the SiFive Unleashed board. Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* clk: sifive: Drop GEMGXL clock driverAnup Patel2019-07-191-1/+0
| | | | | | | | | | The GEMGXL clock driver is now directly part of Cadence MACB ethernet driver in upstream Linux kernel. There is no separate GEMGXL clock driver in upstream Linux kernel hence we drop GEMGXL clock driver from U-Boot as well. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: sifive: fu540: Enable GEMGXL MGMT driverBin Meng2019-06-011-0/+1
| | | | | | | | Enable the new GEMGXL MGMT driver so that GEM 10/100 Mbps works now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: fu540: enable SMPLukas Auer2019-04-081-0/+1
| | | | | | Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: Add SiFive FU540 board supportAnup Patel2019-02-271-0/+42
This patch adds SiFive FU540 board support. For now, only SiFive serial, SiFive PRCI, and Cadance MACB drivers are only enabled. The SiFive FU540 defconfig by default builds U-Boot for S-Mode because U-Boot on SiFive FU540 will run in S-Mode as payload of BBL or OpenSBI. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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