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* common: Move clock functions into a new fileSimon Glass2020-01-171-0/+1
| | | | | | | These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Move device-tree setup functions to fdt_support.hSimon Glass2020-01-171-0/+1
| | | | | | | | These functions relate to setting up the device tree for booting the OS. The fdt_support.h header file supports similar functions, so move these there. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Move some board functions out of common.hSimon Glass2019-12-021-0/+1
| | | | | | | A number of board function belong in init.h with the others. Move them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: ls1021a: drop redundant board_mmc_init()Yangbo Lu2019-11-271-14/+0
| | | | | | | | | The board_mmc_init() defined in board files is actually doing same thing with the cpu_mmc_init() defined in arch/arm/cpu/armv7/ls102xa/cpu.c. So drop it. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* video: fsl_dcu_fb: refactor init functionsIgor Opaniuk2019-07-291-2/+3
| | | | | | | | | | | | Move dcu-related code to fsl_dcu_probe_common, keep in video_hw_init() only legacy video stack (filling GraphicPanel struct etc.). Add wrappers for all init functions, that will let to provide struct fb_info as an additional param (needed for further moving it from the global scope to driver private data struct in DM converted driver). Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
* arm: ls1021atwr: Convert to use driver model TSEC driverBin Meng2019-07-251-38/+0
| | | | | | | | | | | | | | | | | | | | | | Now that we have added driver model support to the TSEC driver, convert ls1021atwr board to use it. This depends on previous DM series for ls1021atwr: http://patchwork.ozlabs.org/patch/561855/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> [Vladimir] Made the following changes: - Added 'status = "disabled";' for all Ethernet ports in ls1021a.dtsi - Fixed the confusion between the SGMII/TBI PCS for enet0 and enet1 - a mistake ported over from Linux. Each SGMII PCS lies on the private MDIO bus of the interface (and the RGMII enet2 has no SGMII PCS). - Added CONFIG_DM_ETH to all ls1021atwr_* defconfigs - Completely removed non-DM_ETH support from ls1021atwr - Changed "compatible" string from "fsl,tsec-mdio" to "fsl,etsec2-mdio" and from "fsl,tsec" to "fsl,etsec2" to match Linux
* armv7: ls102xa: Add workaround for DDR erratum A-008850Alison Wang2019-03-151-0/+2
| | | | | | | | | | Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* arm: ls1021a: Add timer_init() in board_init_f for SPLAlison Wang2018-12-061-0/+1
| | | | | | | | | | | | | | | | | | | | I2C is used to access DDR SPD in the DDR initialization for SPL. In i2c_write process, get_timer() will be called. In board_init_f for SPL, timer_init() is not called before. The system counter is not enabled and the counter frequency is not set to 12.5MHz in SPL. The parameters for do_div() are zero too. It could not be found until CONFIG_USE_PRIVATE_LIBGCC is enabled in default. When CONFIG_USE_PRIVATE_LIBGCC is enabled, U-Boot will use its own set of libgcc functions. As the parameters for do_div() are zero, __div0 will be called. Then the processor will stay in an endless loop after calling hang(). This patch will add timer_init() in board_init_f for SPL and fix a series of issues it caused. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv7: fsl: remove sata supportPeng Ma2018-09-271-4/+0
| | | | | | | Remove the old implementation in order to enable DM for sata Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-073-6/+3
| | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
* MAINTAINERS: Switch nxp.com domainFabio Estevam2018-05-011-1/+1
| | | | | | | freescale.com domain is no longer reachable, so switch the maintainers' emails to nxp.com domain instead. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* arm: ls1021atwr: Rework local commands to not be included in SPLTom Rini2018-01-151-46/+45
| | | | | | | | | | | | | | | Move some of the code for the "lane_bank" and "cpld" code local commands so that they are not built for SPL as they can only be used in full U-Boot. This means we can mark a few functions as static as well now. Cc: Alison Wang <alison.wang@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: York Sun <york.sun@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Alison Wang <alison.wang@nxp.com> Tested-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl-lsch2: csu: remove multiple calling functionHou Zhiqiang2017-08-091-1/+0
| | | | | | | | | Function enable_layerscape_ns_access() is alreayd called soc-wide. Remove duplicated calling from individual boards. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [YS: Add commit message] Reviewed-by: York Sun <york.sun@nxp.com>
* arm: ls1021atwr: Enable RGMII TX/RX clock internal delay for AR8033Alison Wang2017-04-241-0/+1
| | | | | | | | | | | | | Since commit ce412b7, RGMII TX clock internal delay is not enabled for AR8033 unconditionally. On LS1021ATWR board, the third port eTSEC3 uses AR8033 in RGMII mode. The TX/RX internal delay needs to be enabled. This patch will set PHY_INTERFACE_MODE_RGMII_ID to enable RGMII TX/RX clock internal delay for AR8033 on the third port. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Convert CONFIG_FSL_DCU_FB to KconfigSanchayan Maity2017-04-141-1/+1
| | | | | | | | | Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and convert it to Kconfig. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Reviewed-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Alison Wang <alison.wang@nxp.com>
* NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUSTTom Rini2017-01-241-0/+2
| | | | | | | | | Introduce board/freescale/common/Kconfig so that we have a single place for CONFIG options that are shared between ARM and PowerPC NXP platforms. Cc: York Sun <york.sun@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: ls1021a: improve the core frequency to 1.2GHZYuan Yao2016-11-212-2/+2
| | | | | | | Change core clock to 1.2GHz in the configurations for SD and NAND boot. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv7: LS1021a: enable i-cache in start.SXiaoliang Yang2016-10-061-0/+6
| | | | | | | | | | Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First stage of u-boot can run faster after that. There is a description about skip lowlevel init in board/freescale/ls1021atwr/README. Signed-off-by: Xiaoliang Yang <xiaoliang.yang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv7:ls1021a: Enable workaround for DDR erratum A-009942Shengzhou Liu2016-09-141-1/+6
| | | | | Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl-layerscape: Add workaround for PCIe erratum A010315Hou Zhiqiang2016-09-141-0/+4
| | | | | | | | | | As the access to serders protocol unselected PCIe controller will hang. So disable the R/W permission to unselected PCIe controller including its CCSR, IO space and memory space according to the serders protocol field of RCW. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: fsl-layerscape: move forward the non-secure access permission setupHou Zhiqiang2016-09-141-4/+0
| | | | | | | | | | Move forward the basic non-secure access enable operation, so the subsequent individual device access permission can override it. And collect the dispersed callers in board level, and then move them to SoC level. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* board/freescale: Update MAINTAINERS filesYork Sun2016-08-021-0/+4
| | | | | | Update maintainers for secure boot targets. Signed-off-by: York Sun <york.sun@nxp.com>
* ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implementionHongbo Zhang2016-07-262-0/+26
| | | | | | | | | | | | | | | | | This patch implements PSCI functions for ls102xa SoC following PSCI v1.0, they are as the list: psci_version, psci_features, psci_cpu_suspend, psci_affinity_info, psci_system_reset, psci_system_off. Tested on LS1021aQDS, LS1021aTWR. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: ls1021atwr: Add SD secure boot targetSumit Garg2016-07-261-0/+7
| | | | | | | | | | | | | | Add SD secure boot target for ls1021atwr. Implement board specific spl_board_init() to setup CAAM stream ID and corresponding stream ID in SMMU. Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* armv7: ls102xa: Move smmu and stream id initialization into the common soc codeAlison Wang2016-02-241-42/+1
| | | | | | | | The initialization for smmu and stream id is moved into the common soc code. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* qe: move drivers/qe/qe.h to include/fsl_qe.hQianyu Gong2016-02-241-1/+1
| | | | | | | | As the QE firmware struct is shared with Fman, move the header file out of drivers/qe/. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-01-281-2/+2
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| * arm: ls1021atwr: Do not wrap pci_eth_init() with CONFIG_TSEC_ENETBin Meng2016-01-281-2/+2
| | | | | | | | | | | | | | The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | secure_boot: enable chain of trust for ARM platformsAneesh Bansal2016-01-271-0/+4
|/ | | | | | | | | | | | | | Chain of Trust is enabled for ARM platforms (LS1021 and LS1043). In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: ls1021a: merge SoC specific code in a separate fileYao Yuan2015-12-131-40/+2
| | | | | | | Create a soc.c file to put the code for soc special settings. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls1021atwr: optimize the deep sleep latencytang yuantian2015-10-301-2/+17
| | | | | | | | | | | | It will take more than 1s when wake up from deep sleep. Most of the time is spent on outputing information. This patch reduced the deep sleep latency by: 1. avoid outputing system informaton 2. remove flush cache after DDR restore 3. skip reloading second stage uboot binary when SD boot Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls1021a: Add sata support on qds and twr boardtang yuantian2015-10-291-0/+12
| | | | | | | | | | Freescale ARM-based Layerscape LS102xA contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls1021aqds and ls1021atwr boards. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv7/ls1021a: move ns_access to common fileMingkai Hu2015-10-291-94/+8
| | | | | | | | | | Config Security Level Register is different between different SoCs, so put the CSL register definition into the arch specific directory. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls1021a: Add QSPI or IFC support in SD bootAlison Wang2015-10-265-22/+25
| | | | | | | | | | | | | | As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported in SD boot now. For the customer's demand, QSPI needs to be supported in SD boot too. This patch adds QSPI or IFC support in SD boot according to the corresponding defconfig. For detail, ls1021atwr_sdcard_ifc_defconfig is used to support IFC in SD boot and ls1021atwr_sdcard_qspi_defconfig is used to support QSPI in SD boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm/ls102xa:add hwconfig setting to support disable unused devicesZhuoyu Zhang2015-09-011-0/+5
| | | | | | | | | | | | | | DEVDISRn registers provides a mechanism for gating clocks of IP blocks that are not used. Here we implement hwconfig option to allow users to disable unused peripherals on the board. For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts, User can enable CONFIG_FSL_DEVICE_DISABLE and set "devdis:esdhc,qdma,edma" in hwconfig, thus ESDHC controller & eDMA/qDMA will be clock gated to save more power. Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ls102xa: etsec: Use proper settings for BE BDsClaudiu Manoil2015-09-011-1/+2
| | | | | | | | | | | | | | | Replace the DMACTRL[LE] hack with recommended settings for ETSECDMAMCR to get the same end effect - obtaining big-endian buffer descriptors and frame data for eTSEC. The reset / default value for ETSECDMAMCR is preserved, excepting the BD and FR bits which are cleared to enable the BE mode in accordance with the H/W specifications. Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA" Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Tested-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv7/ls1021a: allow OCRAM access permission as R/W in SPLAlison Wang2015-08-031-85/+92
| | | | | | | | | On LS1021A Rev2.0, OCRAM's security level needs to be changed to non-secure access for SD boot. This patch will allow OCRAM access permission as R/W in SPL. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv7/ls1021atwr: program the regulator for deep sleepchenhui zhao2015-08-031-0/+34
| | | | | | | | Program the external regulator to switch off voltage in deep sleep. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv7/ls1021atwr: added deep sleep support in ubootTang Yuantian2015-08-031-3/+65
| | | | | | Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm/ls102xa: Add little-endian mode support for audio IPsAlison Wang2015-07-201-0/+3
| | | | | | | | As SCFG_ENDIANCR register is added to choose little-endian or big-endian for audio IPs on Rev2.0 silion, little-endian mode is selected. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm/ls1021a: Remove ccsr_ddr from immap_ls102xa.hYork Sun2015-05-201-0/+1
| | | | | | | | | ccsr_ddr structure is already defined in fsl_immap.h. Remove this duplicated define. Move fixed timing into ls1021atwr.h. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com>
* pci/layerscape: remove unnecessary pcie_layerscape.hMinghuan Lian2015-04-211-3/+2
| | | | | | | | | | The patch uses the common function name ft_pci_setup to replace ft_pcie_setup, then removes unnecessary pcie_layerscape.h because all the functions have been declared in common.h. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ls1021atwr: add hwconfig setting to do pin muxYao Yuan2015-04-211-0/+78
| | | | | | | | | Freescale LS1021ATWR share some pins. Hwconfig option is used to allows users to choose the pin functions. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> [York Sun: revised commit message] Reviewed-by: York Sun <yorksun@freescale.com>
* arm/ls102xa:Add support of conditional workaround implementation as per SoC verAlison Wang2015-04-211-6/+21
| | | | | | | | For LS102xA, some workarounds are only used in VER1.0, so silicon version detection are added for QDS and TWR boards. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls1021x: Add support for initializing CAAM's stream idAlison Wang2015-02-241-0/+21
| | | | | | | | | There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id for using the same SMMU3 on LS1021A. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls102xa: Add LPUART support for LS1021ATWR boardAlison Wang2015-01-231-0/+1
| | | | | | | | This patch adds LPUART support for LS1021ATWR board. For ls1021atwr_nor_lpuart_defconfig, LPUART is used as the console. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls102xa: Update snoop settings for CCI-400Alison Wang2015-01-231-10/+15
| | | | | | | | | | | CAAM is connected to CCI-400 S0 slave interface. Disable snooping for S0 will cause CAAM self test failure. This patch is to enable snooping for S0 slave interface. These CCI-400 operations are moved to board_early_init_f() to be initialized earlier. For S4 slave interface, issuing of snoop requests and DVM message requests are enabled. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* imx: ls102xa: Remove reference to gdataSimon Glass2015-01-201-3/+0
| | | | | | | | The global_data pointer (gd) has already been set before board_init_f() is called. We should not assign it again. We should also not use gdata since it is going away. Signed-off-by: Simon Glass <sjg@chromium.org>
* ARM: ls102xa: Setting device's stream id for SMMUs.Xiubo Li2014-12-111-0/+21
| | | | | | | | | | | | LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ARM: ls102xa: allow all the peripheral access permission as R/W.Xiubo Li2014-12-111-0/+91
| | | | | | | | | | | | | | | The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data. For now we configure all the peripheral access permissions as R/W. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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