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* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-06-031-1/+4
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| * armv8: layerscape: Make U-Boot EL2 safeYork Sun2017-06-011-1/+4
| | | | | | | | | | | | | | | | | | When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com>
* | dm: Use dm.h header when driver mode is usedSimon Glass2017-06-012-1/+2
|/ | | | | | | | This header includes things that are needed to make driver build. Adjust existing users to include that always, even if other dm/ includes are present Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_CMD_HASH to KconfigSimon Glass2017-05-221-0/+1
| | | | | | | | | | This converts the following to Kconfig: CONFIG_CMD_HASH Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Rework slightly, enable on some boards again] Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_CMD_ESBC_VALIDATE to KconfigSimon Glass2017-05-221-0/+9
| | | | | | | | This converts the following to Kconfig: CONFIG_CMD_ESBC_VALIDATE Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* lib: move hash CONFIG options to KconfigTom Rini2017-05-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support using hardware acceleration.") created entries for CONFIG_SHA1, CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL. However, no defconfig has migrated to it. Complete the move by first adding additional logic to various Kconfig files to select this when required and then use the moveconfig tool. In many cases we can select these because they are required to implement other drivers. We also correct how we include the various hashing algorithms in SPL. This commit was generated as follows (after Kconfig additions): [1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL [2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL Note: We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously because there is dependency between them. Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Chander Kashyap <k.chander@samsung.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Heiko Schocher <hs@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_SPL_BOARD_INIT to KconfigLey Foon Tan2017-05-221-0/+1
| | | | | | | | | This converts the following to Kconfig: CONFIG_SPL_BOARD_INIT Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> [trini: Update the Kconfig logic] Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_CMD_BLOB to KconfigSimon Glass2017-04-301-0/+1
| | | | | | | | | This converts the following to Kconfig: CONFIG_CMD_BLOB Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add imply CMD_BLOB under CHAIN_OF_TRUST] Signed-off-by: Tom Rini <trini@konsulko.com>
* armv7: ls1021a: Drop macro CONFIG_LS102XAYork Sun2017-04-173-5/+5
| | | | | | Use CONFIG_ARCH_LS1021A instead. Signed-off-by: York Sun <york.sun@nxp.com>
* arm: ls1043ardb: Add SD secure boot targetRuchika Gupta2017-04-171-0/+4
| | | | | | | | | | | | | | | | | | | | - Add SD secure boot target for ls1043ardb. - Implement FSL_LSCH2 specific spl_board_init() to setup CAAM stream ID and corresponding stream ID in SMMU. - Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. - CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM (128K) where 32K are reserved for use by boot ROM and 6K for secure boto header. - Error messages during SPL boot are limited to error code numbers instead of strings to reduce the size of SPL image. Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl: Secure Boot: Enable IE (Key extention) FeatureUdit Agarwal2017-03-281-16/+72
| | | | | | | | | | | | | | | | | | | | | | | For validating images from uboot (Such as Kernel Image), either keys from SoC fuses can be used or keys from a verified table of public keys can be used. The latter feature is called IE Key Extension Feature. For Layerscape Chasis 3 based platforms, IE table is validated by Bootrom and address of this table is written in scratch registers 13 and 14 via PBI commands. Following are the steps describing usage of this feature: 1) Verify IE Table in ISBC phase using keys stored in fuses. 2) Install IE table. (To be used across verification of multiple images stored in a static global structure.) 3) Use keys from IE table, to verify further images. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-lsch3: Update VID supportPriyanka Jain2017-03-141-12/+162
| | | | | | | | | | | | | | VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like LS2088A, LS2080A differs from existing logic. -VDD voltage array is different -Registers are different -VDD calculation logic is different Add new function adjust_vdd() for LSCH3 compliant SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Arpit Goel <arpit.goel@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Freescale/NXP: Migrate CONFIG_FSL_CAAM to defconfigsTom Rini2017-03-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | In some cases this is absolutely required, so select this for some secure features. This also requires migration of RSA_FREESCALE_EXP Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Saksham Jain <saksham.jain@nxp.freescale.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUSTTom Rini2017-01-241-0/+4
| | | | | | | | | Introduce board/freescale/common/Kconfig so that we have a single place for CONFIG options that are shared between ARM and PowerPC NXP platforms. Cc: York Sun <york.sun@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-01-192-0/+96
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| * pmic: pmic_mc34vr500: Add APIs to set/get SWx voltHou Zhiqiang2017-01-182-0/+96
| | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | SPL: Adjust more debug prints for ulong entry_pointTom Rini2017-01-111-1/+1
|/ | | | | | | | With entry_point now being an unsigned long we need to adapt the last two debug prints to use %lX not %X. Fixes: 11e1479b9e67 ("SPL: make struct spl_image 64-bit safe") Signed-off-by: Tom Rini <trini@konsulko.com>
* powerpc: MPC8641HPCN: Remove macro CONFIG_MPC8641HPCNYork Sun2016-11-231-1/+1
| | | | | | Use TARGET_MPC8641HPCN from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8610HPCD: Remove macro CONFIG_MPC8610HPCDYork Sun2016-11-231-1/+1
| | | | | | Use TARGET_MPC8610HPCD from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P5040DS: Remove macro CONFIG_P5040DSYork Sun2016-11-231-2/+2
| | | | | | Use CONFIG_TARGET_P5040DS instead. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P5020DS: Remove macro CONFIG_P5020DSYork Sun2016-11-231-2/+2
| | | | | | Use CONFIG_TARGET_P5020DS instead. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P4080DS: Remove macro CONFIG_P4080DSYork Sun2016-11-231-2/+2
| | | | | | Use CONFIG_TARGET_P4080DS instead. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P3041DS: Remove macro CONFIG_P3041DSYork Sun2016-11-231-2/+2
| | | | | | Use CONFIG_TARGET_P3041DS instead. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P2041RDB: Remove macro CONFIG_P2041RDBYork Sun2016-11-231-1/+1
| | | | | | Use CONFIG_TARGET_P2041RDB instead. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P1022DS: Remove macro CONFIG_P1022DSYork Sun2016-11-231-1/+1
| | | | | | Use CONFIG_TARGET_P1022DS instead. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8572DS: Remove macro CONFIG_MPC8572DSYork Sun2016-11-232-2/+2
| | | | | | Use CONFIG_TARGET_MPC8572DS instead. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8569MDS: Remove macro CONFIG_MPC8569MDSYork Sun2016-11-231-1/+1
| | | | | | Use CONFIG_TARGET_MPC8569MDS instead. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8555CDS: Remove macro CONFIG_MPC8555CDSYork Sun2016-11-231-1/+1
| | | | | | Use CONFIG_TARGET_MPC8555CDS instead. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8541CDS: Remove macro CONFIG_MPC8541CDSYork Sun2016-11-231-1/+1
| | | | | | Replace with CONFIG_TARGET_MPC8541CDS from Kconfig. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8536DS: Remove macro CONFIG_MPC8536DSYork Sun2016-11-232-2/+2
| | | | | | Use CONFIG_TARGET_MPC8536DS instead. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8544DS: Remove macro CONFIG_MPC8544DSYork Sun2016-11-231-1/+1
| | | | | | Use CONFIG_TARGET_MPC8544DS instead. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8548CDS: Remove macro CONFIG_MPC8548CDSYork Sun2016-11-231-1/+1
| | | | | | Use CONFIG_TARGET_MPC8548CDS instead. Signed-off-by: York Sun <york.sun@nxp.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-10-121-38/+14
|\ | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/ls1021aqds.h include/configs/ls1021atwr.h
| * fsl_sec_mon: Update driver for Security MonitorSumit Garg2016-10-061-38/+14
| | | | | | | | | | | | | | | | | | | | | | Update the API's for transition of Security Monitor states. Instead of providing both initial and final states for transition, just provide final state for transition as Security Monitor driver will take care of it internally. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> [York Sun: Reformatted commit message slightly] Reviewed-by: York Sun <york.sun@nxp.com>
* | spi: Move freescale-specific code into a private headerSimon Glass2016-10-061-0/+13
|/ | | | | | | | | | | | | | At present there are two SPI functions only used by freescale which are defined in the spi_flash.h header. One function name matches an existing generic SPL function. Move these into a private header to avoid confusion. Arcturus looks like it does not actually support SPI, so drop the SPI code from that board. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-09-263-19/+86
|\ | | | | | | | | | | | | trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * armv8: ls1046aqds: Add LS1046AQDS board supportShaohui Xie2016-09-141-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1046AQDS Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add LS1 PSCI system suspendHongbo Zhang2016-09-141-1/+34
| | | | | | | | | | | | | | | | The deep sleep function of LS1 platform, is mapped into PSCI system suspend function, this patch adds implementation of it. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: csu: add an API to set R/W permission to PCIeHou Zhiqiang2016-09-141-0/+28
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: csu: add an API to set individual device access permissionHou Zhiqiang2016-09-141-14/+20
| | | | | | | | | | | | | | | | Add this API to make the individual device is able to be set to the specified permission. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arch, board: squash lines for immediate returnMasahiro Yamada2016-09-231-3/+1
|/ | | | | | | | Remove unneeded variables and assignments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com> Reviewed-by: Angelo Dureghello <angelo@sysam.it>
* SECURE_BOOT: Enable chain of trust in SPL frameworkSumit Garg2016-07-261-1/+33
| | | | | | | | | | | Override jump_to_image_no_args function to include validation of u-boot image using spl_validate_uboot before jumping to u-boot image. Also define macros in SPL framework to enable crypto operations. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPLSumit Garg2016-07-211-0/+56
| | | | | | | | | | | | | | | | As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* board: freescale: common: Add flag for LBMAP brdcfg reg offsetAbhimanyu Saini2016-06-031-2/+9
| | | | | | | | | | | Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP configuration register instead of hardcoding it in set_lbmap() function. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* board: freescale: common: Conditionally compile IFC QXIS funcAbhimanyu Saini2016-06-031-0/+2
| | | | | | | | | | Check if qixis supports memory-mapped read/write before compiling IFC based qixis read/write functions. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* board: ls102xa: Fix ICID setupVincent Siles2016-06-031-2/+5
| | | | | | | LS102A ref manual dictates that ICID have to be written to the MSB of the ICID register, not to the LSB. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
* arm: uniform usage of u32 in ls102x caam configVincent Siles2016-05-181-1/+1
| | | | | | | Mix usage of uint32_t and u32 fixed in favor of u32. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: Fix SCFG ICID reg addressesVincent Siles2016-05-181-2/+2
| | | | | | | | | | | | | On the LS102x boards, in order to initialize the ICID values of masters, the dev_stream_id array holds absolute offsets from the base of SCFG. In ls102xa_config_ssmu_stream_id, the base pointer is cast to uint32_t * before adding the offset, leading to an invalid address. Casting it to void * solves the issue. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Fix various typos, scattered over the code.Robert P. J. Day2016-05-051-2/+2
| | | | | | | | | | | | | Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller
* armv8/ls2080ardb: Enable VID supportRai Harninder2016-03-291-1/+14
| | | | | | | | This patch enable VID support for ls2080ardb platform. It uses the common VID driver. Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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