summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeFilesLines
...
* | arm: Remove unused _relocate argumentsIvan Gorinov2018-07-194-8/+2
| | | | | | | | | | | | EFI image handle and system table are not used in _relocate(). Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
* | x86: Remove unused _relocate argumentsIvan Gorinov2018-07-193-7/+2
| | | | | | | | | | | | EFI image handle and system table are not used in _relocate(). Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
* | arm/arm64: bitops: fix find_next_zero_bit to be compat with arm64Grygorii Strashko2018-07-191-28/+13
| | | | | | | | | | | | | | | | Current implementation of find_next_zero_bit() is incompatible with arm64. Hence fix it by using BITS_PER_LONG define instead of constants and use generic ffz() implementation. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
* | boards: amlogic: Fix boards READMENeil Armstrong2018-07-191-1/+1
| | | | | | | | | | | | Fix typos and update the supported devices for all Amlogic boards. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | boards: amlogic: Add FriendlyElec NanoPi K2 board supportThomas McKahan2018-07-192-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds platform code for the FriendlyElec NanoPi K2 board based on a Meson GXBB (S905) SoC with the Meson GXBB configuration. This initial submission only supports: - UART - MMC/SDCard - Ethernet - Reset Controller - Clock controller Cc: Yuefei Tan <yftan@friendlyarm.com> Signed-off-by: Thomas McKahan <tonymckahan@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | ARM: dts: sync meson-gxbb-nanopi-k2 from Linux 4.17Neil Armstrong2018-07-192-0/+324
| | | | | | | | | | | | Get the meson-gxbb-nanopi-k2.dts file from Linux 4.17. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | env: common: accept flags on reset to default envYaniv Levinsky2018-07-191-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | The function set_default_env() sets the hashtable flags for import_r(). Formally set_default_env() doesn't accept flags from its callers. In practice the caller can (un)set the H_INTERACTIVE flag, but it has to be done using the first character of the function's string argument. Other flags like H_FORCE can't be set by the caller. Change the function to accept flags argument. The benefits are: 1. The caller will have to explicitly set the H_INTERACTIVE flag, instead of un-setting it using a special char in a string. 2. Add the ability to propagate flags from the caller to himport(), especially the H_FORCE flag from do_env_default() in nvedit.c that currently gets ignored for "env default -a -f" commands. 3. Flags and messages will not be coupled together. A caller will be able to set flags without passing a string and vice versa. Please note: The propagation of H_FORCE from do_env_default() does not introduce any functional changes, because currently himport_r() is set to destroy the old environment regardless if H_FORCE flag is set or not. More changes are needed to utilize the propagation of H_FORCE. Signed-off-by: Yaniv Levinsky <yaniv.levinsky@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* arm: zynq: spl: fix FPGA initializationLuis Araneda2018-07-191-0/+3
| | | | | | | | | | | | commit 4aba5fb857c1 ("arm: zynq: Rework FPGA initialization") moved FPGA initialization from board_init() to arch_early_init_r(), which is not called as part of the SPL Fix this by calling arch_early_init_r() in the spl_board_init() function, so the FPGA is correctly initialized Signed-off-by: Luis Araneda <luaraneda@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add QSPI flash mini u-boot configurationSiva Durga Prasad Paladugu2018-07-192-0/+80
| | | | | | | | | | Add configuration files/dtses for mini u-boot configuration which runs on smaller footprint of internal memory. This configuration has only required qspi flash support and it uses DCC as serial. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm: zynq: Add parallel NOR flash mini u-boot configuration for zynqSiva Durga Prasad Paladugu2018-07-192-0/+89
| | | | | | | | | Add configuration files/dtses for mini u-boot configuration which runs on smaller footprint OCM memory. This configuration only has required parallel nor flash support. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm: zynq: Add Nand flash mini u-boot configuration for zynqSiva Durga Prasad Paladugu2018-07-192-0/+81
| | | | | | | | | Add configuration files/dtses for mini u-boot configuration which runs on smaller footprint of memory. This configuration has only required nand flash support. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* lib: fdtdec: Rename routine fdtdec_setup_memory_size()Siva Durga Prasad Paladugu2018-07-192-2/+2
| | | | | | | | | | | This patch renames the routine fdtdec_setup_memory_size() to fdtdec_setup_mem_size_base() as it now fills the mem base as well along with size. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* microblaze: Do not force saving variables to flashMichal Simek2018-07-191-1/+0
| | | | | | | There is no reason to save variables to flash only. Select option via Kconfig instead. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Convert generic platform to DM gpioMichal Simek2018-07-193-13/+9
| | | | | | | | | | | | | | | | | | | | | | | | Converting GPIO to DM requires to do changes in reset subsystem that's why support for Microblaze soft reset via sysreset and GPIO sysreset support was added. These two patches enables enabling GPIO DM. Microblaze soft reset is bind at last reset method. GPIO reset is handled via sysreset with adding this fragment to DT. gpio-restart { compatible = "gpio-restart"; gpios = <&reset_gpio 0 0 0>; /* 3rd cell ACTIVE_HIGH = 0, ACTIVE_LOW = 1 */ }; hard-reset-gpio property is not documented and also handled. Conversion is required. Unfortunately do_reset is required for SPL that's why use only soft microblaze reset for now. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: xilinx: Setup default number of chipselects for zcu100Michal Simek2018-07-191-0/+2
| | | | | | | | There is only one chipselect on each connector. Define it directly in board dts file. There should be an option to use more chipselects via gpios. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Cosmetic changes in Microblaze related filesShreenidhi Shedi2018-07-191-40/+54
| | | | | Signed-off-by: Shreenidhi Shedi <yesshedi@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Do not call timer init that earlyMichal Simek2018-07-191-0/+4
| | | | | | | | | | Timer needs to be converted to DM but as of now it can't be called so early because intc controller is not ready. Call it later in board_r.c. Before this patch timer_init is called twice which is wrong. The patch is blocking initialization before relocation. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* microblaze: Use default implementation from include/linux/io.hMichal Simek2018-07-191-3/+0
| | | | | | | There is no reason not to use default ioremap/iounmap io functions. The patch remove Microblaze macros. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* xilinx: zynq: Add support to secure imagesSiva Durga Prasad Paladugu2018-07-192-0/+2
| | | | | | | | | | | | | | | | This patch basically adds two new commands for loadig secure images. 1. zynq rsa adds support to load secure image which can be both authenticated or encrypted or both authenticated and encrypted image in xilinx bootimage(BOOT.bin) format. 2. zynq aes command adds support to decrypt and load encrypted image back to DDR as per destination address. The image has to be encrypted using xilinx bootgen tool and to get only the encrypted image from tool use -split option while invoking bootgen. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm/arm64: zynq/zynqmp: pass the PS init file as a kconfig variableLuca Ceresoli2018-07-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot needs to link ps7_init_gpl.c on Zynq or psu_init_gpl.c on ZynqMP (PS init for short). The current logic to locate this file for both platforms is: 1. if a board-specific file exists in board/xilinx/zynq[mp]/$(CONFIG_DEFAULT_DEVICE_TREE)/ps?_init_gpl.c then use it 2. otherwise use board/xilinx/zynq/ps?_init_gpl.c In the latter case the file does not exist in the U-Boot sources and must be copied in the source tree from the outside before starting the build. This is typical when it is generated from Xilinx tools while developing a custom hardware. However making sure that a board-specific file is _not_ found (and used) requires some trickery such as removing or overwriting all PS init files (e.g.: the current meta-xilinx yocto layer). This generates a few problems: * if the source tree is shared among different out-of-tree builds, they will pollute (and potentially corrupt) each other * the source tree cannot be read-only * any buildsystem must add a command to copy the PS init file binary * overwriting or deleting files in the source tree is ugly as hell Simplify usage by allowing to pass the path to the desired PS init file in kconfig variable XILINX_PS_INIT_FILE. It can be an absolute path or relative to $(srctree). If the variable is set, the user-specified file will always be used without being copied around. If the the variable is left empty, for backward compatibility fall back to the old behaviour. Since the issue is the same for Zynq and ZynqMP, add one kconfig variable in a common place and use it for both. Also use the new kconfig help text to document all the ways to give U-Boot the PS init file. Build-tested with all combinations of: - platform: zynq or zynqmp - PS init file: from XILINX_PS_INIT_FILE (absolute, relative path, non-existing), in-tree board-specific, in board/xilinx/zynq[mp]/ - building in-tree, in subdir, in other directory Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Nathan Rossi <nathan@nathanrossi.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2018-07-1741-920/+3666
|\
| * sunxi: Enable eMMC on Libre Computer Board ALL-H3-CC boardsChen-Yu Tsai2018-07-171-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Libretech ALL-H3-CC has a high density connector for attaching an eMMC module. The module form factor and connection is specific to Libretech, and has provisions for split vmmc/vqmmc (core and I/O) voltage supplies, but this board does not wire the vqmmc side. The H2+/H3/H5 SoCs do not support alternate I/O voltages for eMMC either. Only 3.3V is supported. A specific module that ties vqmmc to vmmc, with both at 3.3V, must be used. Given that a) eMMC is not designed to be hotplugged, b) power is always provided on the pins, and c) MMC controllers can deal with missing cards, we can enable this by default. If a module is attached it will be picked up by the system. The device tree change was also submitted to the Linux Kernel and has already been queued up for 4.19. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * configs: Bananapi_M2_Ultra: enable gigabit ethernetLothar Felten2018-07-161-0/+16
| | | | | | | | | | | | | | | | | | | | | | Enable the gigabit ethernet for the Bananapi M2 Ultra board. Tested on BananaPi M2 Berry (R40), custom board (V40) Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
| * sunxi: R40: add gigabit ethernet devicetree nodeLothar Felten2018-07-161-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a device tree node for the Allwinner R40/V40 GMAC gigabit ethernet interface. The R40 SoC does not use the syscon register for GMAC settings. The gigabit ethernet interface can only be routed to a fixed set of pins. Updated to match the Linux kernel's device tree. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
| * sunxi: R40: add gigabit ethernet clocksLothar Felten2018-07-161-1/+9
| | | | | | | | | | | | | | | | | | | | | | Add clock control entries for the gigabit interface of the Allwinner R40/V40 CPU Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
| * dm: sunxi: Use DM for MMC and SATA on all A10 boardsAdam Sampson2018-07-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | Use the driver model for MMC and SATA, in preparation for CONFIG_BLK defaulting to y. Tested on A10 Cubieboard. Signed-off-by: Adam Sampson <ats@offog.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * sunxi: DT: A64: add proper SoPine baseboard device treeAndre Przywara2018-07-163-1/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the defconfig for the SoPine baseboard was added, there wasn't any proper DT for the board yet, so we used the Pine64 DT as a placeholder. Copy the DT file(s) meanwhile added in Linux over to U-Boot, and use them in our defconfig. This is as of v4.18-rc3, exactly Linux commit: commit 7d556bfc49adddf2beb0d16c91945c3b8b783282 Author: Jagan Teki <jagannadh.teki@gmail.com> Date: Mon Dec 4 10:23:07 2017 +0530 arm64: allwinner: a64-sopine: Fix to use dcdc1 regulator instead of vcc3v3 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: DT: H3: update board .dts files from LinuxAndre Przywara2018-07-1615-161/+604
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the .dts file for the various boards with an Allwinner H3 SoC. This is as of v4.18-rc3, exactly Linux commit: commit 721afaa2aeb860067decdddadc84ed16f42f2048 (HEAD) Merge: 7c00e8ae041b 87815dda5593 Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Mon Jun 11 17:57:38 2018 -0700 Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc This also includes the OrangePi Zero .dts, which technically has an Allwinner H2+ SoC. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: DT: H5: update board .dts files from LinuxAndre Przywara2018-07-166-63/+536
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the .dts file for the various boards with an Allwinner H5 SoC. This is as of v4.18-rc3, exactly Linux commit: commit af5d05bdc99c211729cba0a3d5417bccfa308caf Author: Neil Armstrong <narmstrong@baylibre.com> Date: Tue Apr 24 13:47:14 2018 +0200 arm64: dts: allwinner: Add dts file for Libre Computer Board ALL-H3-CC H5 ver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: DT: update device tree files for Allwinner H3 and H5 SoCsAndre Przywara2018-07-1618-554/+986
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the device tree files from the Linux tree as of v4.18-rc3, exactly Linux commit: commit 55c5ba5e49a0a124ed416880e8227b493474495e Author: Chen-Yu Tsai <wens@csie.org> Date: Tue Apr 24 19:34:22 2018 +0800 arm64: dts: allwinner: h5: Add cpu0 label for first cpu Since the H3 and H5 are very similar (aside from the actual ARM cores), they share most the SoC .dtsi and thus have to be updated together. One tiny change is the removal of the "arm/" prefix from the include path in the sun50i-h5.dtsi, which is needed because we don't share the same sophisticated DT directory layout of Linux. Also we need to fix up the board .dts files already, since the .dtsi removes some pins, so the .dts can't reference them anymore. This is to maintain bisectability. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: DT: A64: update board .dts files from LinuxAndre Przywara2018-07-168-72/+900
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the .dts files for the various boards with an Allwinner A64 SoC. This is as of v4.18-rc3, exactly Linux commit: commit 818668055c9d588c9a9d151e3b258ed1adacba0b Author: Jagan Teki <jagan@amarulasolutions.com> Date: Mon Apr 23 12:02:39 2018 +0530 arm64: dts: allwinner: a64: bananapi-m64: add usb otg It updates the existing DT files, adds the newly added axp803.dtsi and removes our temporary kludge file to get Ethernet support in U-Boot. I left the amarula-relic alone, as this DT has not reached mainline yet. The changes are not critical anyway, and the next sync will fix this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: DT: A64: update device tree file for Allwinner A64 SoCAndre Przywara2018-07-162-79/+287
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updates the device tree file from the the Linux tree as of v4.18-rc3, exactly Linux commit: commit c1cff65f9b16b31e731e2e75bbe06638c86e1996 Author: Harald Geyer <harald@ccbib.org> Date: Thu Mar 15 16:25:08 2018 +0000 arm64: dts: allwinner: a64: add simplefb for A64 SoC This also pulls in the newly required include files for the clock and reset bindings, also removes the now redundant part from our *-u-boot.dtsi overlay file. I kept the PWM node from U-Boot, as we recently gained this explicitly for U-Boot's own usage and I don't want to regress here. This node is in the queue for mainline Linux already, so the next sync will make it all equal again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* | zynqmp: zcu102: Add qspi driver support for ZynqMP zcu102 boardsSiva Durga Prasad Paladugu2018-07-161-1/+1
|/ | | | | | | | | This patch adds qspi driver support for all ZynqMP ZCU102 boards. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* mach-stm32: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESETLey Foon Tan2018-07-131-1/+1
| | | | | | | | CONFIG_SPL_RESET_SUPPORT has been renamed to CONFIG_SPL_DM_RESET, update this Kconfig file. Fixes: bfc6bae8fa1f ("reset: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET") Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2018-07-1320-84/+1470
|\ | | | | | | | | | | - Update SPDX tag in arch/arm/mach-socfpga/spl_a10.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * arm: socfpga: Fixes: include <debug_uart.h>Ley Foon Tan2018-07-121-0/+1
| | | | | | | | | | | | | | | | | | | | Fix compilation warning when enable CONFIG_DEBUG_UART. arch/arm/mach-socfpga/spl_s10.c: In function ‘board_init_f’: arch/arm/mach-socfpga/spl_s10.c:146:2: warning: implicit declaration of function ‘debug_uart_init’; did you mean ‘part_init’? [-Wimplicit-function-declaration] debug_uart_init(); Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: Fix: Compile MCR instruction on ARM 32-bit onlyLey Foon Tan2018-07-121-0/+2
| | | | | | | | | | | | | | MCR instruction only available in ARM 32-bit. So, compile MCR instruction when ARM 32-bit is enabled. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: dts: socfpga: stratix10: Fix memory nodeLey Foon Tan2018-07-121-2/+2
| | | | | | | | | | | | | | | | Commit 5dfd5607af2114047bd ("ARM: socfpga: Pull DRAM size from DT") get memory size from DT. So, we need to update memory size in memory node. Otherwise, it cause U-boot hang. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * ARM: socfpga: Assure correct ACTLR configurationMarek Vasut2018-07-121-1/+12
| | | | | | | | | | | | | | | | | | | | Make sure the ARM ACTLR register has correct configuration, otherwise the Linux kernel refuses to boot. In particular, the "Write Full Line of Zeroes" bit must be cleared. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
| * ARM: socfpga: Make DRAM node available in SPLMarek Vasut2018-07-121-0/+1
| | | | | | | | | | | | | | | | | | The SPL can also parse the DRAM configuration node to figure out the memory layout, make sure it is available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
| * ARM: socfpga: Pull DRAM size from DTMarek Vasut2018-07-121-1/+3
| | | | | | | | | | | | | | | | Pull the DRAM size from DT instead of hardcoding it into U-Boot. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
| * arm: socfpga: Add do_bridge_reset for Arria 10Ley Foon Tan2018-07-121-0/+9
| | | | | | | | | | | | | | | | | | | | Add do_bridge_reset() function for Arria 10, it is required by misc.c. arch/arm/mach-socfpga/built-in.o: In function `do_bridge': arch/arm/mach-socfpga/misc.c:221: undefined reference to `do_bridge_reset' make[1]: *** [u-boot] Error 1 Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: stratix10: Enable Stratix10 SoC buildLey Foon Tan2018-07-122-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | Add build support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Conflicts: arch/arm/Kconfig arch/arm/mach-socfpga/Kconfig
| * ddr: altera: stratix10: Add DDR support for Stratix10 SoCLey Foon Tan2018-07-122-6/+188
| | | | | | | | | | | | | | Add DDR support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: stratix10: Add timer support for Stratix10 SoCLey Foon Tan2018-07-122-1/+29
| | | | | | | | | | | | | | | | Add timer support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: stratix10: Add SPL driver for Stratix10 SoCLey Foon Tan2018-07-123-0/+323
| | | | | | | | | | | | | | Add SPL driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: Restructure the SPL fileLey Foon Tan2018-07-123-52/+120
| | | | | | | | | | | | | | | | | | Restructure the SPL so each devices such as CV, A10 and S10 will have their own dedicated SPL file. SPL file determine the HW initialization flow which is device specific Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: stratix10: Add MMU support for Stratix10 SoCLey Foon Tan2018-07-122-0/+72
| | | | | | | | | | | | | | | | Add MMU memory mapping table for Stratix SoC. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: stratix10: Add mailbox support for Stratix10 SoCLey Foon Tan2018-07-123-0/+525
| | | | | | | | | | | | | | | | Add mailbox support for Stratix SoC Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: stratix10: Add misc support for Stratix10 SoCLey Foon Tan2018-07-122-0/+134
| | | | | | | | | | | | | | Add misc support such as EMAC and cpu info printout for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
View Lorry Controller Status