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* Merge tag 'u-boot-rockchip-20200531' of ↵WIP/31May2020Tom Rini2020-05-3111-10/+1179
|\ | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Fix mmc of path after syncfrom kernel dts; - Add dwc3 host support with DM for rk3399; - Add usb2phy and typec phy for rockchip platform; - Migrate board list doc to rockchip.rst; - Add rk3399 Pinebook Pro board support; - Update dram_init in board_init and add memory node in SPL;
| * rockchip: spl: do full dram_init instead of only probingHeiko Stuebner2020-05-311-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Parts of later SPL may need RAM information as well, so do full dram_init() call, which includes the existing dram probing but also initializes the ram information in gd. dram_init() from sdram.c does the following steps: - uclass_get_device(UCLASS_RAM, ...) like the current code - ret = ram_get_info(dev, &ram); - gd->ram_size = ram.size; CONFIG_SPL_RAM already makes sure that sdram.c gets compiled and thus no other variant of dram_init() can exist. So it's the same functionality as before and only adds that the SPL now aquires knowledge about the amount of available ram, which it didn't know about before. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: Add initial support for the Pinebook Pro laptop from Pine64.Peter Robinson2020-05-312-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specification: - Rockchip RK3399 - 4GB Dual-Channel LPDDR4 - eMMC socket - mSD card slot - 128Mbit (16Mb) SPI Flash - AP6256 for 11AC WiFi + BT5 - 14 inch 1920*1080 eDP MiPi display - Camera - USB 3.0, 2.0 ports - Type-C port with alt-mode display (DP 1.2) and 15W charge - DC 5V/3A - optional PCIe slot for NVMe SSD drive Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Tested-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * arm: dts: rockchip: Add initial DT for Pinebook ProPeter Robinson2020-05-312-0/+1097
| | | | | | | | | | | | | | Sync initial support for Pinebook Pro device tree from Linux 5.7-rc1. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * ARM: dts: rk3399-evb: usb3.0 host supportFrank Wang2020-05-301-0/+13
| | | | | | | | | | | | | | | | | | Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host for Rockchip RK3399 Evaluation Board. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm: mach-rockchip: bind sub-nodes for rk3399_sysconFrank Wang2020-05-291-0/+3
| | | | | | | | | | | | | | | | | | | | There are some sub-nodes under the grf DT, so add bind callback function in rk3399 syscon driver to scan them recursively. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rk3399-nanopi4: Add u-boot,spl-boot-orderJagan Teki2020-05-291-0/+6
| | | | | | | | | | | | | | | | Add u-boot,spl-boot-order as sdhci and sdmmc for booting from eMMC and SD card. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: Fix spl mmc boot device ofpathJagan Teki2020-05-294-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux v5.7-rc1 dts(i) sync has changed the sdmmc node from dwmmc@fe320000 to mmc@fe320000 and this ofpath is being used in rockchip spl bootdevice code. So, update the ofpath with a new node name and prefix "same-as-spl" to missing u-boot,spl-boot-order. Bug log: U-Boot SPL 2020.07-rc2-00256-g9c5fef5774 (May 24 2020 - 20:20:43 +0530) Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices Fixes: 167efc2c7a46 ("arm64: dts: rk3399: Sync v5.7-rc1 from Linux" Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | arm: dts: meson-gxl: fix USB gadget by adding missing nodes for U-BootNeil Armstrong2020-05-295-4/+24
| | | | | | | | | | | | | | | | | | | | The khadas-vim, khadas-vim2, libretech-ac & libretech-*-pc boards were missing DT tweak to enable USB gadget. Add them to their -u-boot.dtsi files and include the right gxl-u-boot.dtsi. Fixes: a19e8a0f03 ("arm: dts: meson-gxl: Add USB Gadget nodes for U-Boot") Reported-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | arm: dts: khadas-vim3: include meson-g12-common-u-boot.dtsi to enable HDMI ↵Neil Armstrong2020-05-291-0/+2
|/ | | | | | | | | output Include the common g12 u-boot tweaks to permit enabling video output tweaks on Khadas VIM3 boards. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2020-05-275-105/+132
|\ | | | | | | | | | | - Fix SPI boot on ds414 (Ezra) - Fix PHY mode definition on armada-3720-uDPU (Jakov) - Convert CRS305-1G-4S to generic version (Luka)
| * arm: mvebu: Convert CRS305-1G-4S board to CRS3xx-98DX3236Luka Kovacic2020-05-273-103/+121
| | | | | | | | | | | | | | | | | | | | | | Convert the CRS305-1G-4S board to CRS3xx-98DX3236 to enable easier implementation of new CRS3xx series boards, based on Marvell Prestera 98DX3236. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jakov Petrina <jakov.petrina@sartura.hr>
| * arm: mvebu: armada-3720-uDPU: fix PHY mode definition to sgmii-2500Jakov Petrina2020-05-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f49ac7e1c4 switched the default PHY speed to 3.125Gbit to resolve issues with SFP modules. However, U-Boot does not have a "2500base-x" phy-mode. Resolve this by using "sgmii-2500" instead. Signed-off-by: Jakov Petrina <jakov.petrina@sartura.hr> Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de>
| * arm: mvebu: ds414: add u-boot,dm-pre-reloc to spi0Ezra Buehler2020-05-271-0/+9
| | | | | | | | | | | | | | | | | | Without this U-Boot-specific property, booting on the Synology DS414 (or DS214+) fails in SPL. The spi0 DT node is not scanned, as a result the SPI flash cannot be found. Signed-off-by: Ezra Buehler <ezra@easyb.ch> Reviewed-by: Stefan Roese <sr@denx.de>
* | cbfs: Don't require the CBFS size with cbfs_init_mem()Simon Glass2020-05-271-2/+1
| | | | | | | | | | | | | | | | The size is not actually used since it is present in the header. Drop this parameter. Also tidy up error handling while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: coreboot: add SMBIOS cbmem entry parsingChristian Gmeiner2020-05-273-0/+27
| | | | | | | | | | Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: apl: Use devicetree for FSP-S configurationBernhard Messerklinger2020-05-275-387/+1439
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A the moment the FSP-S configuration is a mix of hard coded values and devicetree properties. This patch makes FSP-S full configurable from devicetree by adding binding properties for all FSP-S parameters. Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral) Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: apl: Use devicetree for FSP-M configurationBernhard Messerklinger2020-05-276-164/+924
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A the moment the FSP-M configuration is a mix of hard coded values and devicetree properties. This patch makes FSP-M full configurable from devicetree by adding binding properties for all FSP-M parameters. Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral) [sjg: Fix a build error for coral] Signed-off-by: Simon Glass <sjg@chromium.org> [bmeng: Add __maybe_unused to fsp_update_config_from_dtb()] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabledBernhard Messerklinger2020-05-271-21/+25
|/ | | | | | | | | | Only load VBT if it's present in the u-boot.rom. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral) Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: Move all SMP related SBI calls to SBI_v01Atish Patra2020-05-262-22/+20
| | | | | | | | | | | SMP support for S-mode U-Boot is enabled only if SBI_V01 is enabled. There is no point in supporting SMP related (IPI and fences) SBI calls when SBI_V02 is enabled. Modify all the SMP related SBI calls to be defined only for SBI_V01. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge tag 'ti-v2020.07-rc3' of ↵WIP/25May2020Tom Rini2020-05-2511-16/+141
|\ | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Enable DM_ETH on omap3_logic board - Enable Caches in SPL for K3 platforms - Enable backup boot mode support for J721E - Update the DDR timings for AM654 EVM - Add automated tests for RX-51
| * arm: mach-k3: Enable dcache in SPLJan Kiszka2020-05-194-0/+38
| | | | | | | | | | | | | | | | | | | | Add support for enabling dcache already in SPL. It accelerates the boot and resolves the risk to run into unaligned 64-bit accesses. Based on original patch by Lokesh Vulta. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: mach-k3: j721e_init: Add support for backup boot modesAndreas Dannenberg2020-05-193-2/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | When the boot of J721E devices using the primary bootmode (configured via device pins) fails a boot using the configured backup bootmode is attempted. To take advantage of the backup boot mode feature go ahead and add support to the J721E init code to determine whether the ROM code performed the boot using the primary or backup boot mode, and if booted from the backup boot mode, decode the bootmode settings into the appropriate U-Boot mode accordingly so that the boot can proceed. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
| * ARM: omap3_logic boards: Convert to DM_ETHAdam Ford2020-05-194-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the converstion of SMC911x to DM, this can facilitate the omap3 boards from LogicPD (now called Beacon EmbeddedWorks) to be converted. There isn't a clean solution to doing this in phases, so the boards are all being done together to avoid breaking functionality. Because the GPMC bus hasn't been converted, the -u-boot.dtsi node needs to show the address of the ethernet controller for each board. The board file, which is common betwen the OMAP35 and DM37 SOM LV and Torpedo boards, can remove the manual ethernet initialization, but it still needs to register the address and GPMC configuration for the Ethernet controller which is now being moved around to board_late_init(). Lastly, this patch updates the various config files to add the reference for DM_ETH and remove the SMC address, which is now fetched from the newly created device tree nodes. Signed-off-by: Adam Ford <aford173@gmail.com>
| * ddr: k3-am654: EMIF Tool update to 2.02 for IO optimizations and fixesPraneeth Bajjuri2020-05-191-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | EMIF tool for AM65x [1] is now updated from rev 1.98 to 2.02 This update includes * Optimizations in IO configuration. * Fix for byte enablement in GCR registers. * Fixes for PG2.0 including ZQ control. [1]: http://www.ti.com/lit/zip/sprcah7 Acked-by: James Doublesin <doublesin@ti.com> Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
* | sandbox: move compression option to KconfigMichael Walle2020-05-251-0/+2
| | | | | | | | | | | | | | | | CONFIG_BZIP2 and CONFIG_GZIP_COMPRESSED are Kconfig options. Select them by CONFIG_SANDBOX instead of setting them in configs/sandbox.h. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
* | armv8: cache_v8: fix mmu_set_region_dcache_behaviourPeng Fan2020-05-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | The enum dcache_optoion contains a shift left 2 bits in the armv8 case already. The PMD_ATTRINDX(option) macro will perform a left shift of 2 bits. Perform a right shift so that in the end we get the correct value. [trini: Reword the commit message] Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | Merge git://git.denx.de/u-boot-usbWIP/22May2020Tom Rini2020-05-221-0/+2
|\ \ | | | | | | | | | | | | | | | - DM support for OMAP - DWC3 fix - Typo fix in eth/r8152
| * | usb: ehci-omap: Add Support for DM_USB and OF_CONTROLAdam Ford2020-05-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The omap3.dtsi file shows the usbhshost node with two sub-nodes for ohci and ehci. This patch file creates the usbhshost, and pulls the portX-mode information. It then locates the EHCI sub-node, and initializes the EHCI controller with the info pulled from the usbhshost node. There is still more to do since there isn't an actual link between the 'phys' reference and the corresponding phy driver, and there is no nop-xceiv driver yet. In the meantime, the older style reference to CONFIG_OMAP_EHCI_PHYx_RESET_GPIO is still needed to pull the phy out of reset until the phy driver is completed and the phandle reference is made. Signed-off-by: Adam Ford <aford173@gmail.com>
* | | Merge tag 'u-boot-rockchip-20200522' of ↵Tom Rini2020-05-224-1/+33
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Fix rk3288 chromebook veyron support; - Add pcie driver support for rk3399; - other fixes for rk3399 boards
| * | | rockchip: rk3328: rock64 - fix gen3 SPL hangKurt Miller2020-05-221-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the same approach as ROC-RK3328-CC which enables SPL GPIO, pinctl and regulator support. This allows the gen3 board to boot through SPL and does not break gen2 in the process. Signed-off-by: Kurt Miller <kurt@intricatesoftware.com> Acked-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | | rockchip: spl-boot-order: do not attempt to access fdt if OF_PLATDATAUrja Rannikko2020-05-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gd->fdt_blob is null if using OF_PLATDATA in SPL, which causes a hang after f0921f5098 ("fdt: Sync up to the latest libfdt"). We use the same test that is used in spl_common_init on whether to call fdtdec_setup to unconditionally avoid linking in the fdt-using code when not necessary and thus reduce SPL size. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | | rockchip: spl: veyron speedy boots from SPIUrja Rannikko2020-05-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently speedy was forgotten from this list of veyron devices. Fixes: 49105fb7ed ("rockchip: add common spl board file") Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | | rockchip: Enable PCIe/M.2 on rk3399 board w/ M.2Jagan Teki2020-05-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable PCIe/M.2 support on - NanoPC-T4 - ROC-RK3399-PC Mezzanine boards. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | | rockchip: rk3399: enable spl-fifo-mode for sdmmcDeepak Das2020-05-221-0/+3
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | adapting commit fa2047c47310 ("rockchip: rk3328: enable spl-fifo-mode for emmc and sdmmc") for rk3399. Since mmc to sram can't do dma, add patch to prevent aborts transferring TF-A parts. Signed-off-by: Deepak Das <deepakdas.linux@gmail.com>
* | | ARM: uniphier: remove board_eth_init()Masahiro Yamada2020-05-221-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This platform completely migrated to CONFIG_DM_ETH. board_eth_init() is only called from net/eth_legacy.c Remove the legacy hook. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: delete or replace <common.h> includesMasahiro Yamada2020-05-2236-36/+8
| | | | | | | | | | | | | | | | | | | | | | | | <common.h> pulls in a lot of bloat. <common.h> is unneeded in most of places. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | ARM: uniphier: drop #include <log.h> againMasahiro Yamada2020-05-225-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I do not understand the changes made to these files by commit f7ae49fc4f36 ("common: Drop log.h from common header"). git show f7ae49fc4f36 -- arch/arm/mach-uniphier/ None of them uses the log function feature. Simply revert the changes made to these files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | ARM: uniphier: drop #include <init.h> again from umc-pxs2.cMasahiro Yamada2020-05-221-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I do not understand the change made to this file by commit 691d719db718 ("common: Drop init.h from common header"). git show 691d719db718 -- arch/arm/mach-uniphier/dram/umc-pxs2.c This file does not call or define any functions declared in <init.h> Simply revert the change made to this file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | ARM: uniphier: remove #include <net.h> again from micro-support-card.cMasahiro Yamada2020-05-221-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I do not understand the changes made to this file by commit 90526e9fbac4 ("common: Drop net.h from common header"). git show 90526e9fbac4 -- arch/arm/mach-uniphier/micro-support-card.c The necessary declaration is already included by <netdev.h> at line 112. It also moved the <dm/of.h> inclusion, but I do not understand the motivation of doing so, either. Simply revert the changes made to this file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: include <asm/system.h> instead of <asm/cache.h> from psci.cMasahiro Yamada2020-05-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I do not understand the change made to this file by commit 90526e9fbac4 ("common: Drop net.h from common header"). git show 90526e9fbac4 -- arch/arm/mach-uniphier/arm32/psci.c It added <asm/cache.h> while this file does not call the standard cache functions at all. All the uniphier-specific cache functions, uniphier_cache_*() are declared in cache-uniphier.h, which is already included from this file. Including <asm/system.h> is sensible to fix the -Wmissing-prototypes warnings because this file defines psci_cpu_on and psci_system_reset(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | ARM: uniphier: select DM_ETHMasahiro Yamada2020-05-221-0/+1
|/ / | | | | | | | | | | | | | | drivers/net/smc911x.c has been converted to DM. select DM_ETH to enable it for all the UniPhier platform boards. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge git://git.denx.de/u-boot-shWIP/21May2020Tom Rini2020-05-219-1/+18
|\ \ | | | | | | | | | | | | - Enable -ffunction-sections / -fdata-sections --gc-sections to SH - RCar Gen3 updates
| * | sh: Enable ffunction-sections and fdata-sectionsMarek Vasut2020-05-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable these two options to let compiler eliminate unused code. On R2Dplus, this results in considerable amount of saved space: text data bss dec hex filename - 266580 13196 39076 318852 4dd84 u-boot + 220214 12797 38745 271756 4258c u-boot Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Tom Rini <trini@konsulko.com>
| * | ARM: dts: rmobile: Enable eMMC DDR52 modes on Gen3 Salvator-X(S),ULCB,EbisuMarek Vasut2020-05-207-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Enable DDR52 modes, since the SD core supports correct switching now. For completeness, list HS200 modes, however those were already enabled. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | ARM: dts: rmobile: Reserve space in R-Car Gen3 DTsMarek Vasut2020-05-201-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reserve 4 kiB of space in R-Car Gen3 DTs when those DTs are compiled to permit patching in OpTee-OS /firmware node, /reserved-memory node and possibly also additional /memory@ nodes. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqWIP/20May2020Tom Rini2020-05-2046-310/+1201
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | - Add DM_ETH support for lx2160aqds, ls2080aqds, ls1088aqds - QSI related fixes on ls1012a, ls2080a, ls1046a, ls1088a, ls1043a based platforms - Bug-fixes/updtaes related to ls1046afrwy, fsl-mc, msi-map property
| * | | arm: dts: ls2080aqds: add CONFIG_MULTI_DTB_FIT supportIoana Ciornei2020-05-195-70/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for selecting the appropriate DTS file depending on the SERDES protocol used. The fsl-ls2080a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol. This patch adds the necessary DPMAC nodes (DPMAC 1-8) for protocol 42 (0x2A) on SD#1. Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | arm: dts: ls1088aqds: add CONFIG_MULTI_DTB_FIT supportIoana Ciornei2020-05-197-120/+271
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for selecting the appropriate DTS file depending on the SERDES protocol used. The fsl-ls2088a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol. This patch adds support for the on-board ports (DPMAC 1,2 and 4,5) found on the SERDES protocols 21(0x15) and 29(0x1d) for SD#1. On the LS1088AQDS board EMDIO1 is used with two onboard RGMII PHYs (Realtek RTL8211FD-CG), as well as 2 input/output connectors for mezzanine cards. Configuration signals from the Qixis FPGA control the routing of the external MDIOs. Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one of the 2 IO slots. As a consequence, a new node is added to describe register 0x54 as a MDIO mux controlled with child nodes describing all the IO slots as MDIO buses. Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | arm: dts: lx2160aqds: add nodes describing possible mezzanine cardsIoana Ciornei2020-05-1916-178/+670
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device trees describing possible uses of mezzanine cards depending on the SERDES protocol employed. This patch adds DPAA2 networking support for the following protocols on each SERDES block: * SD #1: 3, 7, 19, 20 * SD #2: 11 Each SERDES block has a different device tree file per protocol supported, where the IO SLOTs used are enabled and PHYs located on the mezzanine cards are described. Also, dpmac nodes are edited and their associated phy-connection-type and phy-handle are added. Top DTS files are also added for each combination of protocol on the 3 SERDES blocks. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
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