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* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellWIP/16Oct2020Tom Rini2020-10-161-0/+2
|\ | | | | | | | | | | - Fix Octeon SPI driver for Octeon TX2 - Fix and enhance Octeon watchdog driver - Misc minor enhancements to Octeon TX/TX2
| * arm: octeontx: Select CLKStefan Roese2020-10-161-0/+2
| | | | | | | | | | | | | | | | | | | | Clock support is needed for all Octeon TX/TX2 boards. This patch selects CONFIG_CLK so that it is available. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
* | arm: fsl-layerscape: Include device_compat.h in soc.cTom Rini2020-10-161-0/+1
|/ | | | | | Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'mmc-2020-10-14' of ↵WIP/15Oct2020Tom Rini2020-10-151-0/+2
|\ | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - fsl_esdhc_imx cleanup - not send cm13 if send_status is 0. - Add reinit API - Add mmc HS400 for fsl_esdhc - Several cleanup for fsl_esdhc - Add ADMA2 for sdhci
| * arm: dts: lx2160ardb: support eMMC HS400 modeYangbo Lu2020-10-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add properties related to eMMC HS400 mode. mmc-hs400-1_8v; bus-width = <8>; They had been already in kernel dts file since the first lx2160ardb dts patch. b068890 arm64: dts: add LX2160ARDB board support Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellWIP/14Oct2020Tom Rini2020-10-145-159/+611
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Octeon TX: Add NAND driver (Suneel) - Octeon TX: Add NIC driver driver (Suneel) - Octeon TX2: Add NIC driver driver (Suneel) - Armada 8040: Add iEi Puzzle-M80 board support (Luka) - Armada A37xx SPI: Add support for CS-GPIO (George) - Espressobin: Use Linux model/compatible strings (Andre) - Espressobin: Add armada-3720-espressobin-emmc.dts from Linux (Andre) - Armada A37xx: Small cleanup of config header (Pali)
| * | arm64: dts: a3720: add support for espressobin with populated emmcAndre Heider2020-10-142-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | Import armada-3720-espressobin-emmc.dts from Linux, but use sdhc1 for emmc, since our dtsi is still based on downstream and sdhc0 is used for the sd card. Signed-off-by: Andre Heider <a.heider@gmail.com>
| * | arm64: dts: armada-3720-espressobin: split common parts to .dtsiAndre Heider2020-10-142-157/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move most of the dts to the new common armada-3720-espressobin.dtsi file, just like Linux, but keep the current, downstream based, version. The dts itself is imported from Linux. Signed-off-by: Andre Heider <a.heider@gmail.com>
| * | arm64: dts: armada-3720-espressobin: use Linux model/compatible stringsAndre Heider2020-10-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Fix the actual board vendor and ease synching dts files from Linux. Signed-off-by: Andre Heider <a.heider@gmail.com> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: Initial iEi Puzzle-M801 supportLuka Kovacic2020-10-142-0/+390
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial U-Boot support for the iEi Puzzle-M801 board based on the Marvell Armada 88F8040 SoC. Currently supported hardware: 1x USB 3.0 4x Gigabit Ethernet 2x SFP+ (with NXP PCA9555 and NXP PCA9544) 1x SATA 3.0 1x M.2 type B 1x RJ45 UART 1x SPI flash 1x EPSON RX8010 RTC Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
* | | arm: enable DM_RNG on QEMU by defaultHeinrich Schuchardt2020-10-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The EFI_RNG_PROTOCOL is needed for address randomization in Linux. We should provide it by default on QEMU. Reported-by: François Ozog <francois.ozog@linaro.org> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | test: sharpen button label unit testHeinrich Schuchardt2020-10-142-8/+8
|/ / | | | | | | | | | | | | | | Using different strings for the device tree node labels and the label property of buttons sharpens the button label unit test. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
* | Merge branch 'for-next' of https://github.com/lftan/u-bootWIP/12Oct2020Tom Rini2020-10-1220-485/+971
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| * arm: dts: socfpga: arria10: Move to use generic handoff dtsiLey Foon Tan2020-10-093-330/+292
| | | | | | | | | | | | | | Move to use generic handoff dtsi (socfpga_arria10-handoff.dtsi) and include the specify generated _handoff.h header file from qts-filter-a10.sh script. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: arria10: Add handoff header for A10 SoCDK SDMMCDalon Westergreen2020-10-091-0/+305
| | | | | | | | | | | | | | | | Add the qts-filter-a10.sh generated handoff header file for the Arria10 SoCDK SDMMC u-boot device tree. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: arria10: Add qts-filter for Arria10 socfpgaDalon Westergreen2020-10-091-0/+141
| | | | | | | | | | | | | | | | | | Add a script to process HPS handoff data and generate a header for inclusion in u-boot specific devicetree addons. The header should be included in the top level of u-boot.dtsi. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: mailbox: Add mailbox retry supportLey Foon Tan2020-10-091-9/+31
| | | | | | | | | | | | | | | | | | | | | | Resend mailbox command for 3 times with 2ms interval in between if it receives MBOX_RESP_TIMEOUT and MBOX_RESP_DEVICE_BUSY response code. Add a wrapper function mbox_send_cmd_common_retry() for retry, change all the callers to use this wrapper function. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
| * arm: socfpga: mailbox: Update mailbox response codesLey Foon Tan2020-10-091-2/+36
| | | | | | | | | | | | | | Sync latest mailbox response codes from SDM firmware. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
| * arm: socfpga: mailbox: Support sending large mailbox commandChee Hong Ang2020-10-091-35/+78
| | | | | | | | | | | | | | | | Mailbox command which is too large to fit into the mailbox FIFO command buffer can be sent to SDM in multiple parts. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: mailbox: Always read mailbox responses before returning statusChee Hong Ang2020-10-091-4/+2
| | | | | | | | | | | | | | | | | | Mailbox driver should always check for the length of the response and read the response data before returning the response status to caller. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: mailbox: Refactor mailbox timeout event handlingChee Hong Ang2020-10-091-4/+9
| | | | | | | | | | | | | | | | Add miliseconds delay when waiting for mailbox event to happen before timeout. This will ensure the timeout duration is predictive. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: soc64: Document down boot_scratch_cold register usageChin Liang See2020-10-091-0/+8
| | | | | | | | | | | | | | | | | | | | | | Document down the usage of boot_scratch_cold register to avoid overlapping of usage in the code for S10 & Agilex. The boot_scratch_cold register is generally used for passing critical system info between SPL, U-Boot and Linux. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: soc64: Add timeout waiting for NOC idle ACKChee Hong Ang2020-10-091-9/+16
| | | | | | | | | | | | | | Add timeout waiting for NOC idle ACK during FPGA bridge disable/enable. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
| * arm: socfpga: agilex: Enable FPGA Full Reconfiguration supportChee Hong Ang2020-10-091-0/+1
| | | | | | | | | | | | | | | | Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM MailboxChee Hong Ang2020-10-092-2/+2
| | | | | | | | | | | | | | | | | | Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: Use DM watchdog timerChee Hong Ang2020-10-096-3/+11
| | | | | | | | | | | | | | | | | | All SoCFPGA platforms (except Cyclone V) are now switching to CONFIG_WDT (driver model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: soc64: Show reset state in SPLChee Hong Ang2020-10-094-0/+25
| | | | | | | | | | | | | | | | | | Print reset state (warm/cold) together with the source (watchdog/MPU) which has triggered the warm reset on S10 & Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: soc64: Add SDM triggered warm reset bit maskChee Hong Ang2020-10-091-2/+9
| | | | | | | | | | | | | | | | | | Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat register when checking for HPS warm reset status. Refactor the warm reset mask macro for clarity purpose. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * sysreset: socfpga: agilex: Enable sysreset supportChee Hong Ang2020-10-091-1/+1
| | | | | | | | | | | | | | Enable sysreset support for Agilex platform. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * sysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to SoC64Chee Hong Ang2020-10-091-1/+1
| | | | | | | | | | | | | | | | Rename the driver from S10 to SoC64 because Intel Agilex platform also using the this SYSRESET SoCFPGA driver for S10. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: soc64: Initialize timer in SPL onlyChee Hong Ang2020-10-091-1/+2
| | | | | | | | | | | | | | | | | | Timer only need to be initialized once in SPL. This patch remove the redundancy of initializing the timer again in U-Boot proper Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: soc64: Remove PHY interface setup from misc arch initChee Hong Ang2020-10-091-83/+2
| | | | | | | | | | | | | | | | 'dwmac_socfpga' driver will setup the PHY interface during probe. PHY interface setup in arch_misc_init() is no longer needed. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | qemu-arm64: Enable POSITION_INDEPENDENTWIP/2020-10-08-misc-board-improvementsAndre Przywara2020-10-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Now that PIE works when U-Boot is started from ROM, let's enable CONFIG_POSITION_INDEPENDENT, which allows to load U-Boot also via ARM Trusted-Firmware's fip.bin to DRAM, without tweaking the configuration. To get a writable initial stack, we need to keep the fixed initial stack pointer, which points to DRAM in our case. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | qemu-arm: Drop ARCH_SUPPORT_TFABOOTAndre Przywara2020-10-081-1/+0
| | | | | | | | | | | | | | | | | | | | CONFIG_ARCH_SUPPORT_TFABOOT was used on the qemu-arm64 platform to guard a tweak to the flash bank configuration. U-Boot now reads the current flash setup from the devicetree, so there is no need for this option anymore. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm64: PIE: Allow fixed stack pointerAndre Przywara2020-10-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently selecting CONFIG_POSITION_INDEPENDENT also forces us to use an initial stack pointer relative to the beginning of the BSS section. This makes some sense, because this should be writable memory anyway. However the BSS section is not cleared or used until later in the setup process (after relocation), so memory nearby might not be available early enough to host the initial stack. This is an issue if U-Boot is loaded from (Flash-)ROM, for instance. Allow CONFIG_INIT_SP_RELATIVE to be turned off by a board's config, to be able to select a fixed stack pointer, for instance in known good DRAM. This will help QEMU utilising PIE, when it's loaded to (Flash-)ROM. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | arm64: PIE: Skip fixups if distance is zeroAndre Przywara2020-10-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When the actual offset between link and runtime address is zero, there is no need for patching up U-Boot early when running with CONFIG_POSITION_INDEPENDENT. Skip the whole routine when the distance is 0. This helps when U-Boot is loaded into ROM, or in otherwise sensitive memory locations. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | arm64: PIE: Do not skip static relocationAndre Przywara2020-10-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we build an arm64 target and enable POSITION_INDEPENDENT, we were skipping our build-time dynamic relocation fixup routine (STATIC_RELA). This was probably done because we didn't need it in this case, as the PIE fixup routine in start.S would take care of that at runtime. However when we now skip this routine (upon detecting that the fixup offset is 0), this might lead to uninitialised pointers. Remove the exception, so that we always do the build-time relocation. NOTE: GNU binutils starting with v2.27.1 do this build-time relocation automatically, to be in-line with other architecures. So on newer toolchains our manual fixup is actually not needed. It doesn't hurt to have it, though, so that we keep compatibility with the popular Linaro toolchains, which lack this feature. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | arm: Kconfig: Explain TFABOOTAndre Przywara2020-10-081-2/+7
| | | | | | | | | | | | | | | | | | | | The CONFIG_TFABOOT option is more about what U-Boot DOES NOT need to do than to support some features. Explain a bit more in the Kconfig help text to avoid misunderstandings. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | riscv: add DT binding for BOOT button on Maix boardHeinrich Schuchardt2020-10-081-0/+11
| | | | | | | | | | | | | | | | | | Add a device tree binding for the BOOT button on the Maix board. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
* | riscv: Add pinmux and gpio bindings for Kendryte K210Sean Anderson2020-10-082-0/+116
| | | | | | | | | | | | | | | | This patch adds the necessary device tree bindings. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Rick Chen <rick@andestech.com>
* | test: dm: Test for default led namingSean Anderson2020-10-081-1/+1
| | | | | | | | | | | | | | | | This modifies the existing led test to check for default led naming as added in the previous patch. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | test: pinmux: Add test for pin muxingSean Anderson2020-10-081-7/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This extends the pinctrl-sandbox driver to support pin muxing, and adds a test for that behaviour. The test is done in C and not python (like the existing tests for the pinctrl uclass) because it needs to call pinctrl_select_state. Another option could be to add a command that invokes pinctrl_select_state and then test everything in test/py/tests/test_pinmux.py. The pinctrl-sandbox driver now mimics the way that many pinmux devices work. There are two groups of pins which are muxed together, as well as four pins which are muxed individually. I have tried to test all normal paths. However, very few error cases are explicitly checked for. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ram: move aspeed ram driver into drivers/ directoryDylan Hung2020-10-082-440/+1
|/ | | | | | | | to improve the maintainability. It is more easier to modify and add configurations of the driver in the centralized ram driver directory. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* Merge tag 'mips-pull-2020-10-07' of ↵WIP/07Oct2020Tom Rini2020-10-0721-14/+11033
|\ | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mips - mips: octeon: add support for DDR4 memory controller - mips: octeon: add support for DWC3 USB - mips: octeon: add support for booting Linux
| * mips: octeon: Add bootoctlinux commandAaron Williams2020-10-073-0/+716
| | | | | | | | | | | | | | | | | | | | | | | | Octeon needs a platform specific cmd to boot the Linux kernel, as specific parameters need to be passed and special handling for the multiple cores (SMP) is needed. Co-developed-by: Stefan Roese <sr@denx.de> Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> [use gd->ram_base instead of gd->bd->bi_memstart] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mips: octeon: Add bootmem supportAaron Williams2020-10-073-0/+1994
| | | | | | | | | | | | | | | | This is needed for Linux booting, as the memory infos need to be passed in this bootmem format to the Linux kernel. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add coremask supportAaron Williams2020-10-073-0/+1119
| | | | | | | | | | | | | | This patch adds the coremask handling functions. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add header cvmx-bootinfo.hAaron Williams2020-10-071-0/+350
| | | | | | | | | | | | | | | | Add header to handle bootinfo support, needed for Octeon Linux kernel booting. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add header cvmx-fuse.hAaron Williams2020-10-071-0/+71
| | | | | | | | | | | | | | Add header to handle Octeon fuse access. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add header octeon-feature.hAaron Williams2020-10-071-0/+442
| | | | | | | | | | | | | | | | This header includes the Octeon feature detection used in many Octeon drivers. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
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