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* drivers: core: ofnode: fix typo in panel timing decodeRaphael Gallais-Pou2023-05-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case where a single timing resolution is implemented in the device-tree, the property is named "panel-timing", as specify in Linux kernel binding file: Documentation/devicetree/bindings/display/panel/panel-common.yaml # Display Timings panel-timing: description: Most display panels are restricted to a single resolution and require specific display timings. The panel-timing subnode expresses those timings. $ref: panel-timing.yaml# display-timings: description: Some display panels support several resolutions with different timings. The display-timings bindings supports specifying several timings and optionally specifying which is the native mode. $ref: display-timings.yaml# Fixes: 0347cc773270 ("drivers: core: ofnode: Add panel timing decode.") Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* Merge branch 'master_rzn1/rzn1' of ↵WIP/14May2023Tom Rini2023-05-148-2/+1156
|\ | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-sh - R-Car RZN1 support
| * board: schneider: add RZN1 board supportRalph Siemsen2023-05-133-0/+627
| | | | | | | | | | | | | | | | | | | | | | Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which are based on the Reneasas RZ/N1 SoC devices. The intention is to support both boards using a single defconfig, and to handle the differences at runtime. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
| * ARM: rmobile: Add support for Renesas RZ/N1 SoCRalph Siemsen2023-05-133-2/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RZ/N1 is a family of SoC devices from Renesas, featuring: * ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3 * Integrated SRAM up to 6MB * Integrated gigabit ethernet switch * Optional DDR2/3 controller * I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD Add basic support for this family, modeled on the existing RZA1. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
| * ARM: dts: add devicetree for Renesas RZ/N1 SoCRalph Siemsen2023-05-131-0/+477
| | | | | | | | | | | | | | | | This is taken directly from Linux kernel 6.3 (commit 457391b0380335d5e9a5babdec90ac53928b23b4) Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
| * ARM: armv7: add non-SPL enable for Cortex SMPENRalph Siemsen2023-05-131-0/+5
| | | | | | | | | | | | | | | | | | | | Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S") added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For platforms not using SPL boot, add the corresponding non-SPL config, so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
* | bootstd: Rename distro and syslinux to extlinuxSimon Glass2023-05-131-2/+2
|/ | | | | | | | | | | | | | We use the terms 'distro' to mean extlinux but they are not really the same. 'Distro' could refer to any method of booting a distribution, whereas extlinux is a particular method. Also we sometimes use syslinux, but it is better to use the same term in all cases. Rename distro to syslinux and also update bootstd uses of syslinux to use extlinux instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: samus: Don't include audio and SATA in TPLSimon Glass2023-05-111-2/+2
| | | | | | | These are not used in TPL so disable the drivers to save space. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Simplify cpu_jump_to_64bit_uboot()Simon Glass2023-05-111-27/+5
| | | | | | | | | | | This copies the cpu_call64() function to memory address and then jumps to it. This seems to work correctly even when called from SPL, which is running from SPI flash. Drop the copy as it is not needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spl: Commit MTRRs only in board_init_f_r()Simon Glass2023-05-111-1/+0
| | | | | | | | | | | | | We don't need to commit the SPI-flash MTRR change immediately, since it is now done in the board_init_f_r(). Also this causes chromebook_link64 to hang, presumably since we are still running from CAR (Cache-as-RAM) in SPL. Coral handles this OK, perhaps since it is running from a different memory area, but it has no effect on Coral anyway. Drop the extra mtrr_commit() in the SPL implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: spl: Avoid using init_cache_f_r() from SPLSimon Glass2023-05-111-1/+2
| | | | | | | | | | | | | This function is used by U-Boot proper. It does not set up MTRRs when SPL is enabled, but we do want this done when it is called from SPL. In fact it is confusing to use the same function from SPL, since there are quite a few conditions there. All init_cache_f_r() really does is commit the MTRRs and set up the cache. Do this in the SPL's version of this function instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Tidy up address for loading U-Boot from SPLSimon Glass2023-05-111-10/+3
| | | | | | | | | Use the binman symbols for this, to avoid hard-coding the value. We could use CONFIG_X86_OFFSET_U_BOOT for the address, but it seems better to obtain the offset and size through the same mechanism. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: spl: Show debugging for BSSSimon Glass2023-05-111-0/+2
| | | | | | | Show the area of memory cleared for BSS, when debugging is enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: mrc: Correct SPL debug messageSimon Glass2023-05-111-1/+1
| | | | | | | | SPL printf() does not normally support %#x so just use %x instead. Hex is expected in U-Boot anyway. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Tidy up availability of string functionsSimon Glass2023-05-112-2/+8
| | | | | | | | | For now, just enable the fast-but-large string functions in 32-boot U-Boot proper only. Avoid using them in SPL. We cannot use then in 64-bit builds since we only have 32-bit assembly. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Support debug UART in 64-bit modeSimon Glass2023-05-111-0/+7
| | | | | | | | The debug UART is already set up in SPL, so there is no need to do anything here. We must provide the (empty) function though. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Ensure LPC is available for GPIO baseSimon Glass2023-05-111-8/+9
| | | | | | | | | | | The bd82x6x_get_gpio_base() does not work if the LPC is not set up. Probe it early to avoid this problem. In chromebook_link64 this problem shows up as an inability to read the GPIO straps for the memory type. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: Emit the arch_cpu_init_dm() even only before relocationSimon Glass2023-05-1114-14/+14
| | | | | | | | | | | | The original function was only called once, before relocation. The new one is called again after relocation. This was not the intent of the original call. Fix this by renaming and updating the calling logic. With this, chromebook_link64 makes it through SPL. Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coreboot: Show unimplemented sysinfo tagsSimon Glass2023-05-112-0/+8
| | | | | | | | | | | | | | | | | | | | | | | Sometimes coreboot adds new tags that U-Boot does not know about. These are silently ignored, but it is useful to at least know what we are missing. Add a way to collect this information. For Brya it shows: Unimpl. 38 41 37 34 42 40 These are: LB_TAG_PLATFORM_BLOB_VERSION LB_TAG_ACPI_CNVS LB_TAG_FMAP LB_TAG_VBOOT_WORKBUF LB_TAG_TYPE_C_INFO LB_TAG_BOARD_CONFIG Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coreboot: Collect the address of the ACPI tablesSimon Glass2023-05-113-0/+15
| | | | | | | | | | | | | | | | At present any ACPI tables created by prior-stage firmware are ignored. It is useful to be able to view these in U-Boot. Pick this up from the sysinfo tables and display it with the cbsysinfo command. This allows the 'acpi list' command to work when booting from coreboot. Adjust the global_data condition so that acpi_start is available even if table-generation is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* acpi: Create a new Kconfig for ACPISimon Glass2023-05-111-0/+2
| | | | | | | | | | | | | | We have several Kconfig options for ACPI, but all relate to specific functions, such as generating tables and AML code. Add a new option which controls including basic ACPI library code, including the lib/acpi directory. This will allow us to add functions which are available even if table generation is not supported. Adjust the command to avoid a build error when ACPIGEN is not enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Adjust search range for sysinfo tableSimon Glass2023-05-111-2/+2
| | | | | | | | | | | | Avoid searching starting at 0 since this memory may not be available, e.g. if protection against NULL-pointer access is enabled. The table cannot be there anyway, since the first 1KB of memory was originally used for the interrupt table and coreboot avoids it. Start at 0x400 instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge tag 'u-boot-rockchip-20230509' of ↵Tom Rini2023-05-0920-131/+2088
|\ | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-rockchip - Rockchip NFC driver update and dev addr pointer api update; - use standard dr_mode for usb driver; - rock pi boards dts update; - Add rk3566 Anbernic boards; - Misc fixes for drivers;
| * rockchip: handle peripheral as well as otg dr_modeJohn Keeping2023-05-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | The OTG port is identified by inspecting the "dr_mode" property which is expected to be "otg" for this port. But it will work just as well as a device controller when dr_mode is set to "peripheral", which may be required if the mode detection pin is not set up correctly and the device controller needs to be programmed to override this. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: use standard dr_mode parsing functionJohn Keeping2023-05-091-3/+9
| | | | | | | | | | | | | | | | | | | | | | Instead of duplicating the string values here, use usb_get_dr_mode() to handle the property lookup and converting the values to an enum. This is implemented with a switch in preparation for the next patch which adds extra handling for peripheral mode. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm: dts: rockchip: rock-3a: drop u-boot,spl-boot-orderFUKAUMI Naoki2023-05-091-1/+0
| | | | | | | | | | | | | | use common one defined in rk356x-u-boot.dtsi. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm: dts: rk356x: Makefile: sortFUKAUMI Naoki2023-05-091-1/+1
| | | | | | | | | | | | | | sort alphanumerically. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm: dts: rockchip: add Radxa ROCK 4C+FUKAUMI Naoki2023-05-094-0/+829
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux commit 246450344dad arm64: dts: rockchip: rk3399: Radxa ROCK 4C+ Add support for Radxa ROCK 4C+ SBC. Key differences of 4C+ compared to previous ROCK Pi 4. - Rockchip RK3399-T SoC - DP from 4C replaced with micro HDMI 2K@60fps - 4-lane MIPI DSI with 1920*1080 - RK817 Audio codec Also, an official naming convention from Radxa mention to remove Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not Radxa ROCK Pi 4C+. Signed-off-by: Stephen Chen <stephen@radxa.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm: dts: rockchip: rock-pi-4: sync with Linux 6.3FUKAUMI Naoki2023-05-095-122/+174
| | | | | | | | | | | | | | | | | | | | sync dts{,i} files for Radxa ROCK Pi 4 series with Linux 6.3. because rk3399-rock-pi-4a.dts is enough for ROCK Pi 4A/B/A+/B+ and ROCK 4SE, delete dts{,i} for ROCK Pi 4B. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3328: Add support for FriendlyARM NanoPi R2CTianling Shen2023-05-093-0/+44
| | | | | | | | | | | | | | | | | | | | | | The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC chip changed from rtl8211e to yt8521s, and otherwise identical to R2S. The device tree is taken from the kernel linux-next branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=004589ff9df5b75672a78b6c3c4cba93202b14c9 Signed-off-by: Tianling Shen <cnsztl@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * board: rockchip: add Anbernic RGXX3 Series DevicesChris Morgan2023-05-065-0/+905
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Anbernic RGxx3 is a "pseudo-device" that encompasses the following devices: - Anbernic RG353M - Anbernic RG353P - Anbernic RG353V - Anbernic RG353VS - Anbernic RG503 The rk3566-anbernic-rgxx3.dtsi is synced with upstream Linux, but rk3566-anbernic-rgxx3.dts is a U-Boot specific devicetree that is used for all RGxx3 devices. Via the board.c file, the bootloader automatically sets the correct fdtfile, board, and board_name environment variables so that the correct devicetree can be passed to Linux. It is also possible to simply hard-code a single devicetree in the boot.scr file and use that to load Linux as well. The common specifications for each device are: - Rockchip RK3566 SoC - 2 external SDMMC slots - 1 USB-C host port, 1 USB-C peripheral port - 1 mini-HDMI output - MIPI-DSI based display panel - ADC controlled joysticks with a GPIO mux - GPIO buttons - A PWM controlled vibrator - An ADC controlled button All of the common features are defined in the devicetree synced from upstream Linux. TODO: DSI panel auto-detection for the RG353 devices (requires porting of DSI controller driver and DSI-DPHY driver to send DSI commands to the panel). Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm: stm32mp: spl: fix function with fdt_addr_t inputJohan Jonker2023-05-061-1/+1
| | | | | | | | | | | | | | | | | | | | The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so fix ofnode_get_addr_size function with fdt_addr_t input to be able to handle both sizes for stm32mp SoC in spl.c file. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * drivers: fix debug string with fdt_addr_t inputJohan Jonker2023-05-061-1/+1
| | | | | | | | | | | | | | | | | | The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so fix some debug strings with fdt_addr_t to be able to handle both sizes. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * drivers: use dev_read_addr_ptr when cast to pointerJohan Jonker2023-05-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use dev_read_addr_ptr instead of the dev_read_addr function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: syscon_rk3288: store syscon platdata in regmapJohan Jonker2023-05-061-0/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | The Rockchip SoC rk3288 has 2 types of device trees floating around. A 64bit reg size when synced from Linux and a 32bit for U-boot. A pre-probe function in the syscon class driver assumes only 32bit. For other odd reg structures the regmap must be defined in the individual syscon driver. Store rk3288 platdata in a regmap before pre-probe during bind. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'for-2023.07-2' of ↵Tom Rini2023-05-079-31/+224
|\ \ | |/ |/| | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-mpc8xx This pull request adds misc fixes for cssi boards and activates CPM relocation in order to enable the use of SCC4 in QMC (QUICC Multi-Channel) mode.
| * powerpc: mpc8xx: Add SMC relocation CPM microcodeChristophe Leroy2023-05-053-0/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to use QMC mode in the CPM, a SCC requires more space in parameter RAM. After SCC1 there is I2C parameter RAM and after SCC2 there is SPI parameter RAM. MPC866 and MPC885 can already relocate I2C and. SPI parameter RAM. But in order to free space after SCC3 and SCC4, SMC1 and SMC2 need to be relocated. In order to do so, a CPM microcode patch is required. Binary data for that patch is copied from Linux kernel. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
| * powerpc: mpc885: Add CPM USB-SOF microcode for CPM15 ERRATAChristophe Leroy2023-05-054-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC885 CPU has the following ERRATA: When the USB controller is configured in Host mode, and the SOF generation (SFTE=1 in USMOD register) is being used, there may be false CRC error indication in other SCCs. Although the data is received correctly, the CRC result will be corrupted. Add capability to load the related microcode to fix it. The microcode binary data is copied from Linux kernel. Other microcode will be added in following patch so make it a Kconfig choice. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
| * powerpc: Force cast on memcpy_toio()Christophe Leroy2023-05-051-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | sparse reports the following warning: CHECK arch/powerpc/cpu/mpc8xx/micropatch_usb_sof.c arch/powerpc/cpu/mpc8xx/micropatch_usb_sof.c:29:9: warning: cast removes address space '<asn:2>' of expression arch/powerpc/cpu/mpc8xx/micropatch_usb_sof.c:30:9: warning: cast removes address space '<asn:2>' of expression This is because of (void *) casts for using memcpy() as a substitute. Do like other architectures, __force the cast to silence the warning Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
| * powerpc: mpc8xx: Reorganise init RAMChristophe Leroy2023-05-042-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using SMC relocation microcode patch or USB-SOF microcode patch will disable DPRAM memory from 0x2000 to 0x2400 and from 0x2f00 to 0x3000. At the time being, init RAM is setup to use 0x2800-0x2e00, but the stack pointer goes beyond 0x2800 and even beyond 0x2400. For the time being we are not going to use any microcode patch that uses memory about 0x3000, so reorganise setup to use: - 0x2800 - 0x2e00 for init malloc and global data and CPM buffers - 0x3000 - 0x3c00 for init stack For more details about CPM dual port ram, see commit b1d62424cb ("powerpc: mpc8xx: redistribute data in CPM dpram") Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
| * powerpc: mpc8xx: CPM parameter RAM can be anywhereChristophe Leroy2023-05-043-17/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | With relocation, CPM parameter RAM can be anywhere in the dual port RAM, so don't split dual port RAM. Remove dparam and dparam16 members of struct comm_proc PROFF_XXX become offsets from the start of dual port RAM, then they are now consistant with the offsets in RPBASE registers. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
* | Merge tag 'fsl-qoirq-2023-5-5' of ↵Tom Rini2023-05-057-309/+1063
|\ \ | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq fsl-ls1088a device tree update enable DM_SERIAL for ten64 check for crypto node first in fdt_fixup_remove_jr
| * | arm: dts: ten64: fix header typo and update copyrightMathew McBride2023-05-051-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Somehow, I managed to typo our company name in the U-Boot and Linux kernel submissions. Fix this and update the copyright year at the same time. Signed-off-by: Mathew McBride <matt@traverse.com.au> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com> Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
| * | arm: dts: ten64: syncronise device tree with LinuxMathew McBride2023-05-052-24/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This synchronises the Linux device tree with U-Boot (cp linux/..../fsl-ls1088a-ten64.dts uboot/..../fsl-ls1088a-ten64.dts), as of Linux v6.2-rc5. Missing from the U-Boot copy previously was the Ethernet PCS definitions (required for linking with PHY in Linux but not used by U-Boot) and various upstream fixes and formatting changes. The board microcontroller (which doesn't have a Linux driver) has been moved to the -u-boot.dtsi, as well as the spi0 quadspi alias (used by U-boot 'sf' but not valid for Linux). Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com> Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
| * | arm: dts: fsl-ls1088a: copy all missing bindings from LinuxMathew McBride2023-05-051-16/+304
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is effectively: cp linux/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi \ u-boot/arch/arm/dts/fsl-ls1088a.dtsi Tested working with Ten64 board (LS1088A) booting openSUSE Tumbleweed. Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com> Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
| * | arm: dts: fsl-ls1088a: move and sync existing bindings to be under /socMathew McBride2023-05-051-81/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our [U-Boot] copy of fsl-ls1088a.dtsi had all the hardware under the top level, until the DM_SERIAL implementation recently. In this commit, remove any remaining devices (that were in U-Boot, but not touched by previous patches in this series) to be under /soc, updating to their upstream (Linux) bindings. The bindings have been copied closest to their relative positions in the Linux version, so the eventual result is that the U-Boot and Linux fsl-ls1088a.dtsi will be identical. The next commit will add the hardware bindings that were not in U-Boot. Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com> Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
| * | arm: dts: fsl-ls1088a: syncronise fsl-mc definition with LinuxMathew McBride2023-05-052-81/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This moves the fsl-mc device tree definition under the /soc node, as well as adding interrupt and IOMMU definitions that were not in U-Boot before. There are slight differences between the two bindings as we add a "simple-mfd" compatible to function under U-Boot's driver model. Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com> Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
| * | arm: dts: fsl-ls1088a: syncronise MDIO+PCS U-Boot definitions with LinuxMathew McBride2023-05-052-16/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Synchronise the MDIO controller definitions with Linux, so the controllers will be usable when passing U-Boot's control FDT to Linux. This also adds the PCS (internal controller) definitions which are not used by U-Boot. Caveat: The kernel definition uses "fsl,fman-memac-mdio", as with other members of the Layerscape family, but U-Boot uses a different driver for the DPAA2 Family devices (LS1088/LS2088/LX2160). So we use "fsl,ls-mdio" as the first compatible string for these devices. Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com> Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
| * | arm: dts: fsl-ls1088a: sync usb controller nodes with LinuxMathew McBride2023-05-052-14/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Synchronise the USB device tree definition with Linux, allowing the U-Boot control FDT to be used to boot a Linux system with working USB. An extra compatible string, "fsl,layerscape-dwc3" is needed for special handling in U-Boot, so has been added to the -u-boot.dtsi file. It might be better to add this to the Linux source bindings. Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com> Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
| * | arm: dts: fsl-ls1088a: move I2C nodes under "soc" and syncronize with LinuxMathew McBride2023-05-051-32/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot's definition for the I2C controllers did not contain any clock information. This resulted in the I2C not functioning when the U-Boot control FDT was passed to Linux. Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com> Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
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