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* x86: acpi: Name fields in FADT in accordance with specificationAndy Shevchenko2017-07-301-3/+2
| | | | | | | | | ACPI specification defines FADT fields marked as reserved in U-Boot. Name these fields in accordance with ACPI specification. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: acpi: Fill OEM revisionAndy Shevchenko2017-07-301-0/+2
| | | | | | | Fill OEM revision field in the tables by U-Boot build date. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: conga-qeval20-qa3-e3845.dts: Enable xHCI support in dtsStefan Roese2017-07-301-0/+3
| | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: dfi-bt700: Add xHCI USB supportStefan Roese2017-07-301-0/+12
| | | | | | | | | | | | | Change from EHCI to xHCI on the DFI BayTrail SoM. The xHCI USB hub is connected to an GPIO on the DFI BayTrail SoM. For correct operation, it needs to get reset upon power-up. Otherwise it may happen that the hub is not detected after a software reboot. This patch also configures this GPIO in the dts for correct operation. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add Intel Edison board filesAndy Shevchenko2017-07-303-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Intel Edison board which is using U-Boot. The patch is based on work done by the following people (in alphabetical order): Aiden Park <aiden.park@intel.com> Dukjoon Jeon <dukjoon.jeon@intel.com> eric.park <eric.park@intel.com> Fabien Chereau <fabien.chereau@intel.com> Felipe Balbi <felipe.balbi@linux.intel.com> Scott D Phillips <scott.d.phillips@intel.com> Sebastien Colleur <sebastienx.colleur@intel.com> Steve Sakoman <steve.sakoman@intel.com> Vincent Tinelli <vincent.tinelli@intel.com> In case we're building for Intel Edison, we must have 4096 bytes of zeroes in the beginning on u-boot.bin. This is done in board/intel/edison/config.mk. First run sets hardware_id environment variable which is read from System Controller Unit (SCU). Serial number (serial# environment variable) is generated based on eMMC CID. MAC address on USB network interface is unique to the board but kept the same all over the time. Set mac address from U-Boot using following scheme: OUI = 02:00:86 next 3 bytes of MAC address set from eMMC serial number This allows to have a unique mac address across reboot and flashing. Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> [bmeng: Add MAINTAINERS file for Intel Edison board] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add Intel Tangier supportFelipe Balbi2017-07-308-0/+301
| | | | | | | | | | | | | | | | | | | | | | | | Add Intel Tangier SoC support. Intel Tangier SoC is a core part of Intel Merrifield platform. For example, Intel Edison board is based on such platform. The patch is based on work done by the following people (in alphabetical order): Aiden Park <aiden.park@intel.com> Dukjoon Jeon <dukjoon.jeon@intel.com> eric.park <eric.park@intel.com> Fabien Chereau <fabien.chereau@intel.com> Scott D Phillips <scott.d.phillips@intel.com> Sebastien Colleur <sebastienx.colleur@intel.com> Steve Sakoman <steve.sakoman@intel.com> Vincent Tinelli <vincent.tinelli@intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* x86: Add dma-mapping.h to architectural codeAndy Shevchenko2017-07-301-0/+41
| | | | | | | | | | | | Some cross-platform drivers rely on this header present. Make it so for x86. It's just a copy'n'paste of arch/arm/include/asm/dma-mapping.h. Suggested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* arch/x86: Select USB before selecting host driverAndy Shevchenko2017-07-301-0/+1
| | | | | | | | | | | | | | Kbuild complains if USB is not selected before any of host driver. warning: (X86) selects USB_EHCI_HCD which has unmet direct dependencies (USB) warning: (X86) selects USB_EHCI_HCD which has unmet direct dependencies (USB) Select it for X86. Fixes: 64d6ac5bc4a9 ("Kconfig: USB: Migrate CONFIG_USB_EHCI_HCD users to Kconfig") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> [bmeng: Update all x86 boards' defconfig files to remove CONFIG_USB] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* Merge git://git.denx.de/u-boot-socfpgaTom Rini2017-07-296-60/+186
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| * arm: socfpga: Add FPGA driver support for Arria 10Tien Fong Chee2017-07-262-0/+102
| | | | | | | | | | | | | | | | Add FPGA driver support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
| * arm: socfpga: Restructure FPGA driver in the preparation to support A10Tien Fong Chee2017-07-263-57/+81
| | | | | | | | | | | | | | | | | | | | | | Move FPGA driver which is Gen5 specific code into Gen5 driver file and keeping common FPGA driver intact. All the changes are still keeping in driver/fpga/ and no functional change. Subsequent patch would move FPGA manager driver from arch/arm into driver/fpga/. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
| * arm: socfpga: Remove unused passing parameter of socfpga_bridges_resetTien Fong Chee2017-07-262-3/+3
| | | | | | | | | | | | | | | | | | | | | | Remove parameter from socfpga_bridges_reset(), and keeping this function for single purpose which is just triggering reset on bridges. socfpga_reset_deassert_bridges_handoff() can be called for releasing reset on any bridges based on the bridge setting defined in fdt. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
* | Merge git://git.denx.de/u-boot-usbTom Rini2017-07-292-4/+3
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| * | x86: minnowmax: Enable USB xHCI supportBin Meng2017-07-281-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BayTrail SoC supports both EHCI and xHCI controllers. However only one host controller (either EHCI or xHCI) can be used. To enable HSIC and SS ports, xHCI must be used. This turns on xHCI support on Intel MinnowMax board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
| * | configs: Remove CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS in all boardsBin Meng2017-07-281-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that EHCD does not use CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS, remove it in all boards' config files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
* | | dm: power: Convert as3722 to driver modelSimon Glass2017-07-281-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert this PMIC driver to driver model and fix up other users. The regulator and GPIO functions are now handled by separate drivers. Update nyan-big to work correct. Three boards will need to be updated by the maintainers: apalis-tk1, cei-tk1-som. Also the TODO in the code re as3722_sd_set_voltage() needs to be completed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lukasz Majewski <lukma@denx.de> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Jetson-TK1 Tested-by: Stephen Warren <swarren@nvidia.com>
* | | tegra: dts: Move stdout-path to /chosenSimon Glass2017-07-281-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This property should be in the /chosen node, not /aliases. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1 Tested-by: Stephen Warren <swarren@nvidia.com>
* | | dm: tegra: Convert clock_decode_periph_id() to support livetreeSimon Glass2017-07-282-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust this to take a device as a parameter instead of a node. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1 Tested-by: Stephen Warren <swarren@nvidia.com>
* | | dm: tegra: Convert USB setup to livetreeSimon Glass2017-07-287-49/+103
| | | | | | | | | | | | | | | | | | | | | | | | Adjust this code to support a live device tree. This should be implemented as a PHY driver but that is left as an exercise for the maintainer. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* | | tegra: tegra124: Add a PMC syscon driverSimon Glass2017-07-284-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PMC can be modelled as a syscon peripheral. Add a driver for this so that it can be accessed by drivers when needed. Enable it for tegra124 boards. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1 Tested-by: Stephen Warren <swarren@nvidia.com>
* | | tegra: spl: Enable debug UARTSimon Glass2017-07-281-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the debug UART in SPL to allow early serial output even if the standard UART does not work (e.g. due to driver model problem). Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1 Tested-by: Stephen Warren <swarren@nvidia.com>
* | | sandbox: remove os_putc() and os_puts()Masahiro Yamada2017-07-281-11/+0
|/ / | | | | | | | | | | | | | | They are unused since commit d8c6fb8cedbc ("sandbox: Drop special case console code for sandbox"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: add u-boot specific dts for rk3036 sdkAndy Yan2017-07-271-0/+11
| | | | | | | | | | | | | | | | | | | | Add this dts to enable debug uart releated devices before relocation. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | rockchip: use puts instead of printf when back to bootromAndy Yan2017-07-271-2/+2
| | | | | | | | | | | | | | | | | | printf will increase the code size more than 1kb, but platform like rk3036 has no enough space for it. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | rockchip: enable SPL_LIBGENERIC for rk3036 based boardsAndy Yan2017-07-271-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | function board_init_f_init_reserve will call memset, which is implemented in lib, and enabled by CONFIG_SPL_LIBGENERIC_SUPPORT in spl stage. To reduce the code size, also enable SPL_TINY_MEMSET. As rk3036 will return to bootrom immediately after dram initialization, there is no need to run DM, so disable SPL_DM_SERIAL. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | sandbox: use CONFIG_VAL(SYS_MALLOC_F_LEN) to distinguish malloc pool size ↵Andy Yan2017-07-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | before relocation SPL and normal u-boot stage use different malloc pool size configuration before relocation, so use CONFIG_VAL(SYS_MALLOC_F_LEN) to fit different boot stage. Signed-off-by: Andy Yan <andyshrk@gmail.com> Changes in v3: - use CONFIG_VAL(), which suggested by Simon Changes in v2: None arch/sandbox/cpu/start.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | microblaze: spl: configure SYS_MALLOC_F_LEN independently for SPL and full ↵Andy Yan2017-07-271-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot Some platforms have very limited SRAM to run SPL code, so there may not be the same amount space for a malloc pool before relocation in the SPL stage as the normal U-Boot stage. Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN, so the size of pre-relocation malloc pool can be configured memory space independently. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixed up commit-message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | powerpc: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-BootAndy Yan2017-07-272-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some platforms have very limited SRAM to run SPL code, so there may not be the same amount space for a malloc pool before relocation in the SPL stage as the normal U-Boot stage. Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN, so the size of pre-relocation malloc pool can be configured memory space independently. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixed up commit-message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | mips: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-BootAndy Yan2017-07-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some platforms have very limited SRAM to run SPL code, so there may not be the same amount space for a malloc pool before relocation in the SPL stage as the normal U-Boot stage. Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN, so the size of pre-relocation malloc pool can be configured memory space independently. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixed up commit-message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | rockchip: rk3399: enable SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT via ↵Philipp Tomsich2017-07-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kconfig SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT were previously enabled through rk3399_common.h. This change implies these options through Kconfig. These need to always be active for the RK3399, as follows: - SPL_SERIAL_SUPPORT is needed to pass the SPL build - SPL_DRIVERS_MISC_SUPPORT is needed to pass the SPL build Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | rockchip: dts: rk3399-puma: put EFI partition entries at 2MBPhilipp Tomsich2017-07-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When creating a EFI/GUID partition map for the RK3399-Q7 through U-Boot, the partition entries should be places at a 1MB offset from the start of the device to give us space for the environment (at 16KB on SD/MMC devices), the SPL stage (at 32KB on SD/MMC devices) and the image payload (at 256KB on SD/MMC devices). This change sets this up through the u-boot,efi-partition-entries-offset /config property in the RK3399-Q7 DTSI. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | rockchip: dts: rk3399-puma: put environment (in MMC/SD configurations) ↵Philipp Tomsich2017-07-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | before SPL As our SPL stage can grow quite large (80KB+ are not unusual) on the RK3399-Q7, the default setting for the environment location (in include/configs/rockchip-common.h) can overlap our SPL. This change finally makes use of the 'u-boot,mmc-env-offset' DTS property to override the environment location and put it at 16KB into the device, which is right before the SPL (located at 32KB). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | rockchip: clk: rk3399: remove unused fields from priv-structuresPhilipp Tomsich2017-07-271-2/+0
| | | | | | | | | | | | | | | | | | | | This removes the unused 'rate' field from both rk3399_pmuclk_priv and rk3399_clk_priv. I didn't bother to check where this came from (i.e. what the historical context of these was), but only verified that these are indeed unused across all code-paths. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | rockchip: clk: rk3368: remove unused fields from rk3368_clk_privPhilipp Tomsich2017-07-271-2/+0
| | | | | | | | | | | | | | | | | | The rk3368_clk_priv has two unused fields: rate, has_bwadj. This removes them as there's no need for either (i.e. has_bwadj is always true for the RK3368, according to its TRM). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | rockchip: spl: make boot0 hook TPL safePhilipp Tomsich2017-07-271-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building for a TPL/SPL setup (e.g. on the RK3368), we need the TPL stage to have the extra space for for the 'Rockchip SPL name' (i.e. 'RK33' word). Yet, the SPL will start execution at its first word (i.e. the first word in the SPL binary needs to be a valid instruction). To make things a bit more involved, CONFIG_SPL_BUILD is defined both for the SPL and the TPL stage. To avoid having to explicitly test for the first stage (TPL, if and only if TPL and SPL are built, SPL otherwise), this commit modifies the sequence to repeat the 'b reset' (instead of reserving 4 bytes of undefined space) at the start of the boot0 hook: if overwritten (and execution starts at the second word), the first instruction is still a 'b reset'... if not overwritten, we start on a 'b reset' as well. This solution wouldn't even require the check whether we are in the SPL/TPL build (i.e. CONFIG_SPL_BUILD), but we leave this check in for documentation purposes. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | rockchip: pwm: add mask for config settingKever Yang2017-07-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | Use mask to clear old setting before direct set the new config, or else there it will mess up the config when it's not the same with default value. Fixes: 3851059 rockchip: Setup default PWM flags Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | rockchip: dts: correct vdd_log setting for firefly-rk3399Kever Yang2017-07-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | Add regulator-init-microvolt for driver to init the regulator, and the min output value is not 800000mV for the PWM2 io domain has changed to VCC3V0 instead of VCC1V8 in rockchip evb, we need to correct it with the value measured when PWM2 output HIGH. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | rockchip: dts: firefly using ddr3 1600Kever Yang2017-07-271-1/+1
| | | | | | | | | | | | | | | | | | | | According to my test, some of firefly-rk3399 hang after dram init when using ddr3-1333 config, while using ddr3-1600 config works for all the board I have test. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | rockchip: phycore: Add ID page of M24C32-D EEPROMWadim Egorov2017-07-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Identification Page (32 byte) is an additional page which can be written and (later) permanently locked in Read-only mode. phyCORE-RK3288 SoMs are using this page to describe the module variant. This page also contains a MAC. Our boards can be equipped with a different amount of EEPROMs. To make this more transparent let's add an alias for the eeprom which stores the module variant. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | rockchip: timer: make register sizes explicitPhilipp Tomsich2017-07-272-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | We are about to reuse the rockchip timer (header file) for 64bit ARMv8 chips, so it seems a good time to make the register sizes explicit by changing from 'unsigned int' to 'u32'. Reorders the header-includes in rk_timer.c to ensure that 'u32' is definded before it is used by 'asm/arch/timer.h'. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | rockchip: dts: rk3229: add dwc2 node for fastbootMeng Dongyang2017-07-272-0/+14
| | | | | | | | | | | | | | | | Add dwc2 node for fastboot to init dwc2 controller. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | Merge git://git.denx.de/u-boot-uniphierTom Rini2017-07-2630-2006/+17
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| * | ARM: uniphier: remove part number info from the boot logMasahiro Yamada2017-07-261-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As is often the case with SoC development, slightly different products (i.e. different part number) are developed based on the same silicon-die. Such fine grained information is unmaintainable. Also, "SoC:" is a better fit that "CPU:". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: remove SPL support for ARMv8 SoCsMasahiro Yamada2017-07-2629-1995/+6
| |/ | | | | | | | | | | | | | | | | | | | | It has been a while since ARM Trusted Firmware supported UniPhier SoC family. U-Boot SPL was intended as a temporary loader that runs in secure world. It is a maintenance headache to support two different boot mechanisms. Secure firmware is realm of ARM Trusted Firmware and now U-Boot only serves as a non-secure boot loader for UniPhier ARMv8 SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge git://git.denx.de/u-boot-mipsTom Rini2017-07-269-182/+237
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| * | MIPS: bootm: Fix broken boot_env_legacy codepathZubair Lutfullah Kakakhel2017-07-251-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes 2 bugs introduced by the following commit 2bb5b63 MIPS: bootm: rework and fix broken bootm code The CONFIG_IS_ENABLED macro prepends 'CONFIG_' Hence, remove CONFIG_ from CONFIG_MIPS_BOOT_ENV_LEGACY usage. Also, 2bb5b63 reworks bootm so that linux_env_legacy runs before linux_cmdline_legacy. However, linux_env_legacy depends on linux_cmdline_legacy running first as linux_cmdline_init initialilzes linux_argp which linux_env_legacy later depends on during its initialization. Reorder the code so that linux_cmdline_legacy runs before linux_env_legacy. Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
| * | MIPS: Stop building position independent codePaul Burton2017-07-258-178/+233
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot has up until now built with -fpic for the MIPS architecture, producing position independent code which uses indirection through a global offset table, making relocation fairly straightforward as it simply involves patching up GOT entries. Using -fpic does however have some downsides. The biggest of these is that generated code is bloated in various ways. For example, function calls are indirected through the GOT & the t9 register: 8f998064 lw t9,-32668(gp) 0320f809 jalr t9 Without -fpic the call is simply: 0f803f01 jal be00fc04 <puts> This is more compact & faster (due to the lack of the load & the dependency the jump has on its result). It is also easier to read & debug because the disassembly shows what function is being called, rather than just an offset from gp which would then have to be looked up in the ELF to discover the target function. Another disadvantage of -fpic is that each function begins with a sequence to calculate the value of the gp register, for example: 3c1c0004 lui gp,0x4 279c3384 addiu gp,gp,13188 0399e021 addu gp,gp,t9 Without using -fpic this sequence no longer appears at the start of each function, reducing code size considerably. This patch switches U-Boot from building with -fpic to building with -fno-pic, in order to gain the benefits described above. The cost of this is an extra step during the build process to extract relocation data from the ELF & write it into a new .rel section in a compact format, plus the added complexity of dealing with multiple types of relocation rather than the single type that applied to the GOT. The benefit is smaller, cleaner, more debuggable code. The relocate_code() function is reimplemented in C to handle the new relocation scheme, which also makes it easier to read & debug. Taking maltael_defconfig as an example the size of u-boot.bin built using the Codescape MIPS 2016.05-06 toolchain (gcc 4.9.2, binutils 2.24.90) shrinks from 254KiB to 224KiB. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | ARM: DTS: stm32: remove useless mr-nbanks propertyPatrice Chotard2017-07-262-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | FMC driver is now able to discover the bank number by parsing bank subnodes. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | ram: stm32: migrate fmc defines in driver filePatrice Chotard2017-07-261-74/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Migrate all FMC defines from arch/arm/include/asm/arch-stm32f7/fmc.h to drivers/ram/stm32_sdram.c This will avoid to add an additionnal arch-stm32xx/fmc.h file when a new stm32 family soc will be introduced. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | clk: stm32f7: remove clock_get()Patrice Chotard2017-07-261-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | All drivers which was using clock_get() are now using clk_get_rate() from clock framework, now it's safe to remove clock_get(). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
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