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* Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2018-10-053-0/+12
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| * ARM: rmobile: Enable PHY framework on Gen3Marek Vasut2018-10-031-0/+1
| | | | | | | | | | | | | | Enable PHY framework on Gen3, this is required for USB EHCI PHY support. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Mark 4-64GiB as DRAM on Gen3Marek Vasut2018-10-031-0/+6
| | | | | | | | | | | | | | | | | | Mark area 0x1_0000_0000 - 0x10_0000_0000 as DRAM on Gen3 as the chip is capable of addressing that and U-Boot can make use of it. This patch prevents exception when accessing those areas. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: dts: rmobile: Reinstate missing i2c6 on PorterMarek Vasut2018-10-031-0/+5
| | | | | | | | | | | | | | | | The I2C6 is used to communicate with the PMIC and it was removed during DT sync with Linux 4.17. Reinstate it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2018-10-053-39/+3
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| * | arm: socfpga: stratix10: add sgmii in phymode setupOoi, Joyce2018-10-031-2/+3
| | | | | | | | | | | | | | | | | | | | | Additional sgmii phymode is added in socfpga_phymode_setup() along with a minor fix for maximum number of GMACs. Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com>
| * | arm: socfpga: Remove unused function socfpga_emac_manage_reset()Ley Foon Tan2018-10-032-37/+0
| |/ | | | | | | | | | | Remove code from the reset manager that is never called. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | Merge tag 'rockchip-for-v2018.11-rc2' of git://git.denx.de/u-boot-rockchipTom Rini2018-10-052-47/+99
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rockchip-focused changes for v2018.11-rc2: - fixes to rkimage for SPL boot via USB - fixes to make_fit_atf.py, incl. entry-point calculation and python3 compatibility - OP-TEE support for ARMv7-based SoCs - fixes to RGMII/GMII selection on the RK3328 Signed-off-by: Tom Rini <trini@konsulko.com>
| * | rockchip: make_fit_atf: make python3 compatibleMian Yousaf Kaukab2018-10-041-44/+45
| | | | | | | | | | | | | | | | | | | | | Make script python3 compatible. No functional changes intended. Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: make_fit_atf: use elf entry pointMian Yousaf Kaukab2018-10-041-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | make_fit_atf.py uses physical address of first segment as the entry point to bl31. It is incorrect and causes following abort when bl31_entry() is called: U-Boot SPL board initTrying to boot from MMC1 "Synchronous Abort" handler, esr 0x02000000 elr: 0000000000000000 lr : 00000000ff8c7e8c x 0: 00000000ff8e0000 x 1: 0000000000000000 x 2: 0000000000000000 x 3: 00000000ff8e0180 x 4: 0000000000000000 x 5: 0000000000000000 x 6: 0000000000000030 x 7: 00000000ff8e0188 x 8: 00000000000001e0 x 9: 0000000000000000 x10: 000000000007fcdc x11: 00000000002881b8 x12: 00000000000001a2 x13: 0000000000000198 x14: 000000000007fdcc x15: 00000000002881b8 x16: 00000000003c0724 x17: 00000000003c0718 x18: 000000000007fe80 x19: 00000000ff8e0000 x20: 0000000000200000 x21: 00000000ff8e0000 x22: 0000000000000000 x23: 000000000007fe30 x24: 00000000ff8d1c3c x25: 00000000ff8d5000 x26: 00000000deadbeef x27: 00000000000004a0 x28: 000000000000009c x29: 000000000007fd90 Fix it by using the entry point from the elf header. Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: add fit source file for pack itb with op-teeKever Yang2018-10-041-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | We package U-Boot and OP-TEE into one itb file for SPL, so that we can support OP-TEE in SPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: make_fit_atf: fix warning unit_address_vs_regKever Yang2018-10-041-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch fix warning: /builddir/BUILD/u-boot-2018.05-rc2/"arch/arm/mach-rockchip/make_fit_atf.py" \ arch/arm/dts/rk3399-firefly.dtb > u-boot.its ./tools/mkimage -f u-boot.its -E u-boot.itb >/dev/null && cat /dev/null u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/uboot@1 has a unit name, but no reg property u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@1 has a unit name, but no reg property u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@2 has a unit name, but no reg property u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@3 has a unit name, but no reg property u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/fdt@1 has a unit name, but no reg property u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /configurations/config@1 has a unit name, but no reg property make[1]: Leaving directory '/builddir/BUILD/u-boot-2018.05-rc2/builds/firefly-rk3399' Reported-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | | arc: Add support for IoT development kitAlexey Brodkin2018-10-053-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DesignWare ARC IoT Development Kit is a versatile platform that includes the necessary hardware and software to accelerate software development and debugging of sensor fusion, voice recognition and face detection designs. More information is avaialble here [1] and here [2]. The board is based on real silicon with ARC EM9D-based Data Fusion IP Subsystem. It sports a rich set of I/O including * DW USB OTG * DW MobileStorage (used for micro SD-card) * GPIO * multiple serial interface including DW APB UART * ADC, PWM and eFlash, SRAM and SPI Flash memory * Real-Time Clock (RTC) * Bluetooth module with worldwide regulatory compliance (FCC, IC, CE, ETSI, TELEC) * On-board 9-axis sensor (gyro, accelerometer and compass) Extensible with Arduino, Pmod, mikroBUS connectors and a 2x18 extension header. One of the most interesting features for developers is built-in Digilent USB JTAG probe so only micro-USB cable is needed! [1] https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_development_kit [2] https://www.synopsys.com/dw/doc.php/ds/cc/iot_dev_kit.pdf Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | | ARC: Implement print_cpuinfo()Alexey Brodkin2018-10-051-1/+34
| | | | | | | | | | | | | | | | | | | | | Once we enable DISPLAY_CPUINFO for ARC we'll see ARC core family and version printed on boot. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | | ARC: Add model property to boards .dtsAlexey Brodkin2018-10-056-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. This way we sync with Linux kernel where we have model set for all ARC boards for quite some time, see [1] 2. Once we enable DISPLAY_BOARDINFO for ARC this info will be printed on boot givin some extra data-point about the board [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=618a9cd06dd471ac232f5b27325b24d26eba5571 Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | | ARC: Don't pre-define CROSS_COMPILEAlexey Brodkin2018-10-051-6/+0
|/ / | | | | | | | | | | | | | | Even though arc-linux- prefix is used in ARC prebuilt tools and in Buildroot there're other options like Linux distro cross-tools etc where prefix is different so let's not rely on this default. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | Merge tag 'rockchip-for-v2018.11' of git://git.denx.de/u-boot-rockchipTom Rini2018-10-032-0/+23
|\ \ | | | | | | | | | Rockchip changes for 2018.11
| * | rockchip: rk3188: explicitly set vcc_sd0 pin to gpio on rk3188-radxarockHeiko Stuebner2018-10-021-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is good practice to make the setting of gpio-pinctrls explicitly in the devicetree, and in this case even necessary. Rockchip boards start with iomux settings set to gpio for most pins and while the linux pinctrl driver also implicitly sets the gpio function if a pin is requested as gpio that is not necessarily true for other drivers. The issue in question stems from uboot, where the sdmmc_pwr pin is set to function 1 (sdmmc-power) by the bootrom when reading the 1st-stage loader. The regulator controlled by the pin is active-low though, so when the dwmmc hw-block sets its enabled bit, it actually disables the regulator. By changing the pin back to gpio we fix that behaviour. [picked from the identical linux patch https://patchwork.kernel.org/patch/10609253/] Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: rk3188: add u-boot-specific mmc propertiesHeiko Stuebner2018-10-021-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dwmmc controllers on rk3188 do not have idma support, so need to use the fifo-mode and it my tests they became confused and stopped working if the frequency was to high. While I only tested in somewhat bigger steps, 32MHz for example hung the controller, while reducing it to 16MHz worked just fine and is reasonably fast to load a kernel from mmc. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | | riscv: allow native compilationHeinrich Schuchardt2018-10-031-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | If environment variable CROSS_COMPILE is not set, this indicates native compilation. In this case we should not set an arbitrary value which is not applicable for 64bit anyway. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | riscv: cosmetic: Reword do_reset() printf message.Rick Chen2018-10-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Sentence "reset unsupported yet" is not grammatically correct and should say "reset not supported yet" instead. Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Signed-off-by: Rick Chen <rick@andestech.com>
* | | riscv: Move do_reset() to a common placeBin Meng2018-10-034-17/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't have a reset method on any RISC-V board yet. Instead of adding the same 'unsupported' message for each CPU variant it might make more sense to add a generic do_reset function for all CPU variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c). Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* | | riscv: Add QEMU virt board supportBin Meng2018-10-034-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged architecture spec v1.10. Both 32-bit and 64-bit builds are supported. Support is pretty much preliminary, only booting to U-Boot shell with the UART driver on a single core. Booting Linux is not supported yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* | | riscv: kconfig: Imply DM support for some common driversBin Meng2018-10-031-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | This implies DM support for some common drivers that are used on RISC-V. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* | | riscv: kconfig: Select DM and OF_CONTROLBin Meng2018-10-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | RISC-V is a pretty new architecture and should support DM and OF_CONTROL by default. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* | | riscv: ae350: Clean up mixed tabs and spaces in the dtsBin Meng2018-10-031-87/+90
| | | | | | | | | | | | | | | | | | | | | | | | There are quite a lot of mixed tabs and spaces in the ae350.dts. Clean them up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* | | riscv: Make start.S available for all targetsBin Meng2018-10-035-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Currently start.S is inside arch/riscv/cpu/ax25/, but it can be common for all RISC-V targets. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* | | riscv: bootm: Pass mhartid CSR value to kernelBin Meng2018-10-031-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far this is hardcoded to zero, and we should read the value from mhartid CSR and pass it to Linux kernel. Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
* | | riscv: Remove CSR read/write defines in encoding.hBin Meng2018-10-031-46/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no reason to keep two versions of CSR read/write defines in encoding.h. We already have one set of defines in csr.h, which is from Linux kernel, and let's drop the one in encoding.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
* | | riscv: Add a helper routine to print CPU informationBin Meng2018-10-034-0/+179
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a helper routine to print CPU information. Currently it prints all the instruction set extensions that the processor core supports. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* | | riscv: Explicitly pass -march and -mabi to the compilerBin Meng2018-10-031-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the compiler flag against which architecture and abi variant the riscv image is built for is not explicitly indicated which means the default compiler configuration is used. But this does not work if we want to build a different target (eg: 32-bit riscv images using a toolchain configured for 64-bit riscv). Fix this by explicitly passing -march and -mabi to the compiler. Since generically we don't use floating point in U-Boot, specify the RV[32|64]IMA ISA and software floating ABI. This also fix some alignment coding style issues. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* | | riscv: Fix coding style issues in the linker scriptBin Meng2018-10-031-30/+28
| | | | | | | | | | | | | | | | | | | | | There are several coding style issues in the linker script. Fix them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* | | riscv: Move the linker script to the CPU root directoryBin Meng2018-10-031-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | The linker script can be shared by all RISC-V targets. Move it to a common place. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* | | riscv: Remove mach typeBin Meng2018-10-032-30/+0
| | | | | | | | | | | | | | | | | | | | | Since the mach_id is not used by RISC-V, remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* | | riscv: bootm: Correct the 1st kernel argument to hart idBin Meng2018-10-031-13/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first argument of Linux kernel is the risc-v core hart id, from which the kernel is booted from. It is not the mach_id, which seems to be copied from arm. While we are here, this also changes the Linux kernel entry parameters' type to support both 32-bit and 64-bit. Note the hart id is hardcoded to zero for now, and we should change to fill in it with the value read from mhartid CSR of the hart which this routine is currently running on. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
* | | riscv: Remove setup.hBin Meng2018-10-033-208/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This was copied from ARM, and does not apply to RISC-V. While we are here, bootm.h is eventually removed as its content is only the inclusion of setup.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* | | riscv: kconfig: Normalize architecture name spellingBin Meng2018-10-032-4/+4
| |/ |/| | | | | | | | | | | | | It's RISC-V that is the official name, not RISCV. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2018-10-021-1/+1
|\ \ | |/ |/| | | | | | | | | This is the PR for SPI-NAND changes along with few spi changes. [trini: Re-sync changes for ls1012afrwy_qspi*_defconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
| * mtd: move NAND files into a raw/ subdirectoryMiquel Raynal2018-09-201-1/+1
| | | | | | | | | | | | | | | | | | NAND flavors, like serial and parallel, have a lot in common and would benefit to share code. Let's move raw (parallel) NAND specific code in a raw/ subdirectory, to ease the addition of a core file in nand/ and the introduction of a spi/ subdirectory specific to SPI NANDs. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2018-09-302-0/+11
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| * | dm: test: Add "/firmware" node scan testRajan Vaja2018-09-292-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a test which verifies that all subnodes under "/firmware" nodes are scanned. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added 'imply FIRMWARE' to sandbox Kconfig to fix test failures, fixed ordering of lines in arch/sandbox/dts/test.dts and test/dm/Makefile, updated #if condition in drivers/firmware/firmware-uclass.c: Signed-off-by: Simon Glass <sjg@chromium.org>
| * | test: Add tests for board uclassMario Six2018-09-291-0/+4
| | | | | | | | | | | | | | | | | | | | | Add tests for the new board uclass. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
* | | dts: db410c: Add bindings for MSM USB phyRamon Fried2018-09-301-0/+7
| | | | | | | | | | | | Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
* | | db410c: serial# env using msm board serialRamon Fried2018-09-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The serial# environment variable needs to be defined so it will be used by fastboot as serial for the endpoint descriptor. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
* | | dts: db410c: add alias for USBRamon Fried2018-09-301-0/+4
| | | | | | | | | | | | | | | | | | Alias is required so req-seq will be filled. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2018-09-292-0/+13
|\ \ \ | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
| * | | video_osd: Add osd sandbox driver and testsMario Six2018-09-282-0/+13
| |/ / | | | | | | | | | | | | | | | | | | Add sandbox driver and tests for the new OSD uclass. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2018-09-29104-6039/+4747
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| * | | ARM: dts: sun8i: Update A23/A33/r16 dts(i) files from Linux-v4.18-rc3Jagan Teki2018-09-2818-232/+338
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update all A23/A33/r16 devicetree dtsi and dtsi files from Linux-v4.18-rc3 with below commits. A23: commit bc3bd041fe766219a44688b182c260064007f0cc Author: Miquel Raynal <miquel.raynal@bootlin.com> Date: Tue Apr 24 17:55:02 2018 +0200 ARM: dts: sun8i: a23/a33: declare NAND pins A33: commit 88fe315d2c0a397ef42d7639addab0e021ae911d Author: Maxime Ripard <maxime.ripard@bootlin.com> Date: Wed Apr 4 11:57:15 2018 +0200 ARM: dts: sun8i: a33: Add the DSI-related nodes r16: commit 9621d0bd1b0d61167e1853ac68cf4869c31bcc96 Author: Miquel Raynal <miquel.raynal@bootlin.com> Date: Tue Apr 24 17:55:03 2018 +0200 ARM: dts: nes: add Nintendo NES/SuperNES Classic Edition support Note: - Drop pinctrl from sun8i-r16-nintendo-nes-classic-edition.dts since sun8i-a23-a33.dtsi is added with Linux sync. - Don't sync non U-Boot supported dts files sun8i-a23-ippo-q8h-v1.2.dts sun8i-a23-ippo-q8h-v5.dts sun8i-a33-et-q8-v1.6.dts sun8i-a33-ippo-q8h-v1.2.dts sun8i-r16-nintendo-nes-classic.dts sun8i-r16-nintendo-super-nes-classic.dts Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | ARM: dts: sun7i: Update A20 dts(i) files from Linux-v4.18-rc3Jagan Teki2018-09-2826-1411/+1447
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update all A10 devicetree dtsi and dtsi files from Linux-v4.18-rc3 with below commit: commit 5d9ef839f874f4e3923c8a9ae7b136c6c3912cd5 Author: Stefan Mavrodiev <stefan@olimex.com> Date: Wed May 16 14:38:08 2018 +0300 ARM: dts: sun7i: Add Olimex A20-SOM-EVB-eMMC board Note: - Update sun7i-a20-primo73.dts as per Linux, since this dts is U-Boot specific. - Drop sun7i-a20-olimex-som-evb-emmc.dts since no board added for this. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
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