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* arm: dts: imx7: sync with LinuxStefan Agner2018-06-271-176/+315
| | | | | | Sync with Linux commit 60cc43fc8884 ("Linux 4.17-rc1"). Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* board: Add support for KEY1 status detection on K+P's HSC|DDC boardsLukasz Majewski2018-06-181-0/+2
| | | | | | | This code provides information if the K+P's imx53 boards had KEY1 pressed. Signed-off-by: Lukasz Majewski <lukma@denx.de>
* board: imx53: Always disable display before starting kernelLukasz Majewski2018-06-181-0/+2
| | | | | | | | | | | | | This patch prevents from the situation where we may end up with garbage displayed on the LCD panel. Such situation occurs when one performs "reboot -f" in Linux and then stop in U-boot (or observe the garbage on the screen during boot up). To prevent from such situation - the PWM pin is configured as GPIO and set to LOW. Signed-off-by: Lukasz Majewski <lukma@denx.de>
* ARM: mxs: let boards override entire dram parameter tableMans Rullgard2018-06-181-7/+7
| | | | | | | | If many values differ from the defaults, overriding the full table is simpler and more space efficient than tweaking it through mxs_adjust_memory_params(). Signed-off-by: Mans Rullgard <mans@mansr.com>
* imx: Enable ACTLR.SMP bit for all i.MX cortex-a7 platformsYe Li2018-06-182-7/+42
| | | | | | | | | | | | | | According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed". ROM sets this bit in normal boot flow, but when in serial download mode, it is not set. Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms, including mx7d, mx6ul/ull and mx7ulp. Signed-off-by: Ye Li <ye.li@nxp.com> [fabio: adapted to U-Boot mainline codebase and make checkpatch happy] Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2018-06-161-2/+4
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| * sunxi: clock: Fix EHCI and OHCI clocks on A64Vasily Khoruzhick2018-06-131-2/+4
| | | | | | | | | | | | | | | | EHCI0 is bit 24, EHCI1 - 25, OHCI0 - 28, OHCI1 - 29 Fixes commit fef73766d9ad ("sunxi: clock: Fix OHCI clock gating for H3/H5") Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
* | Merge tag 'xilinx-for-v2018.07-rc2' of git://git.denx.de/u-boot-microblazeTom Rini2018-06-1510-28/+80
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx fixes for v2018.07-rc2 Zynq: - Fix missing watchdog header - DT fixes ZynqMP: - emmc configuration split - Enable SPD - Fix PMUFW_INIT_FILE logic - Coverity fixes in SoC code timer - Add timer_get_boot_us mmc: - Fix MMC HS200 tuning command serial: - Fix scrabled chars with OF_LIVE
| * | arm64: zynqmp: Check return value in zynqmp_mmio_rawwrite()Michal Simek2018-06-151-1/+5
| | | | | | | | | | | | | | | | | | | | | There should be return value check from zynqmp_mmio_read() in zynqmp_mmio_rawwrite() to make sure that errors are propagated properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm: zynq: Drop #address-cells and #size-cells from gpio-keysMichal Simek2018-06-156-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dtc is showing some warnings and this change was also done in the Linux kernel as "Input: gpio-keys - clean up device tree binding example" with this fragment in commit message "Drop #address-cells and #size-cells, which are not required by the gpio-keys binding documentation, as button sub-nodes are not devices." Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Split emmc configuration into emmc0 and emmc1Siva Durga Prasad Paladugu2018-06-153-15/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch splits the current mini emmc configuration into emmc0 and emmc1 configurations because emmc is probed at boot time and on systems which have only one interface mini configuration is failing on unused interface. This patch also adds required clock node in dts and enables CONFIG_MMC_SDHCI_ZYNQ through defconfig. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge tag 'signed-efi-next' of git://github.com/agraf/u-bootTom Rini2018-06-142-14/+8
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | Patch queue for efi - 2018-06-14 A few minor fixes for the release: - Compile fixes - HI20 relocations for RISC-V - Fix bootefi without load path - Fix Runtime Services with certain compilers
| * | efi_loader: Convert runtime reset from switch to if statementsAlexander Graf2018-06-142-14/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently handle the UEFI runtime reset / power off case handling via a switch statement. Compilers (gcc in my case) may opt to handle these via jump tables which they may conveniently put into .rodata which is not part of the runtime section, so it will be unreachable when executed. Fix this by just converting the switch statement into an if/else statement. It produces smaller code that is faster and also correct because we no longer refer .rodata from efi runtime code. Reported-by: Andreas Färber <aferber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* | | Merge git://git.denx.de/u-boot-x86Tom Rini2018-06-1321-177/+284
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| * | x86: cougarcanyon2: Add missing chipset interrupt informationBin Meng2018-06-131-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | Add Panther Point chipset interrupt pin/PIRQ information, and enable the generation of PIRQ routing table and MP table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: irq: Support discrete PIRQ routing registers via device treeBin Meng2018-06-132-33/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently both pirq_reg_to_linkno() and pirq_linkno_to_reg() assume consecutive PIRQ routing control registers. But this is not always the case on some platforms. Introduce a new device tree property intel,pirq-regmap to describe how the PIRQ routing register offset is mapped to the link number and adjust the irq router driver to utilize the mapping. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: irq: Parse number of PIRQ links from device treeBin Meng2018-06-132-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "intel,pirq-link" property in Intel IRQ router's dt bindings has two cells, where the second one represents the number of PIRQ links on the platform. However current driver does not parse this information from device tree. This adds the codes to do the parse and save it for future use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: efi: payload: Enforce toolchain to generate 64-bit EFI payload stub codesBin Meng2018-06-132-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Attempting to use a toolchain that is preconfigured to generate code for the 32-bit architecture (i386), for example, the i386-linux-gcc toolchain on kernel.org, to compile the 64-bit EFI payload does not build. This updates the makefile fragments to ensure '-m64' is passed to toolchain when building the 64-bit EFI payload stub codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Conditionally build the pinctrl_ich6 driverBin Meng2018-06-134-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | The pinctrl_ich6 driver is currently unconditionally built for all x86 boards. Let's use a Kconfig option to control the build. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: irq: Change LINK_V2N and LINK_N2V to inline functionsBin Meng2018-06-132-10/+34
| | | | | | | | | | | | | | | | | | | | | | | | LINK_V2N and LINK_N2V are currently defines, so they cannot handle complex logics. Change to inline functions for future extension. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: irq: Remove chipset specific irq router driversBin Meng2018-06-1310-129/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present there are 3 irq router drivers. One is the common one and the other two are chipset specific for queensbay and quark. However these are really the same drivers as the core logic is the same. The two chipset specific drivers configure some registers that are outside the irq router block which should really be part of the chipset initialization. Now we remove these specific drivers and make all x86 boards use the common one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: cougarcanyon2: Enable CPU driver and SMP supportBin Meng2018-06-131-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | This enables the 206ax cpu driver on Intel Cougar Canyon 2 board, so that SMP can be supported too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: chromebook_link: Remove dm-pre-reloc property in the cpu nodesBin Meng2018-06-131-5/+0
| | | | | | | | | | | | | | | | | | | | | The 206ax cpu driver does not require pre-relocation flag to work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Drop CONFIG_USBDEBUGBin Meng2018-06-132-20/+0
| | | | | | | | | | | | | | | | | | | | | This is not used anywhere. Clean this up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Enable 206ax cpu driver for FSP buildBin Meng2018-06-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | At present this 206ax cpu driver is only built when FSP is not used. This updates the Makefile to enable the build for both cases. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: cougarcanyon2: Update dts for SPI lock downBin Meng2018-06-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that like Braswell, Intel FSP for IvyBridge requires SPI controller settings to be locked down, as the U-Boot ICH SPI driver fails with the following message on Cougar Canyon 2 board: "ICH SPI: Opcode 9f not found" Update the SPI node property to indicate this fact. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Imply USB_XHCI_HCDBin Meng2018-06-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The Panther Point chipset connected to Ivybridge has xHC integrated, imply it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: baytrail: Correct the comment of IACORE_VIDS bit rangesBin Meng2018-06-131-1/+1
| |/ | | | | | | | | | | | | | | The guaranteed vid bit ranges in IACORE_VIDS MSR is actually [22:16]. This corrects the comment for it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ARM: DTS: resync a3517.dtsi with Linux 4.17Adam Ford2018-06-131-6/+2
| | | | | | | | | | | | | | Linux 4.17 was just released with some minor changes to the am3517.dtsi. This patch re-syncs the file. Signed-off-by: Adam Ford <aford173@gmail.com>
* | ARM64: meson: Sync DT with Linux 4.17Neil Armstrong2018-06-1310-237/+103
|/ | | | | | | | | Synchronize the Linux Device Tree for Amlogic Meson GX boards from Linux 4.17.0 This will enable USB on Amlogic Meson GXL Boards like Khadas VIM, P212 or LibreTech-CC. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2018-06-125-35/+59
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| * LS1012AFRWY: Add Secure Boot supportVinitha V Pillai2018-06-111-0/+1
| | | | | | | | | | | | | | | | | | Added the following: 1. defconfig for LS1012AFRWY Secure boot 2. PfE Validation support Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * board: ls1012a: FRWY-LS1012A board supportBhaskar Upadhaya2018-06-114-1/+58
| | | | | | | | | | | | | | | | | | | | FRWY-LS1012A belongs to LS1012A family with features 2 1G SGMII PFE MAC, Micro SD, USB 3.0, DDR, QuadSPI, Audio, UART. Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> [yorks: rebase and fix SPDX tag] [yorks: fix board/freescale/ls1012afrdm/Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
| * board: Kconfig: Re-Arrangement of PPA firmware and header addressesBhaskar Upadhaya2018-06-081-34/+0
| | | | | | | | | | | | | | | | | | | | | | PPA firmware and header address may vary depending upon different boards, configure ppa firmware and header address in board specific Kconfig. Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm: mvebu: Add Helios4 Armada 38x initial supportDennis Gilmore2018-06-124-0/+423
|/ | | | | | | | | | | The helios4 is built on the SolidRun Armada 38x SOM. The port os based on the ClearFog board, using information from https://github.com/helios-4/u-boot-marvell as well as dtb input from https://github.com/helios-4/linux-marvell Signed-off-by: Dennis Gilmore <dennis@ausil.us> Signed-off-by: Dennis Gilmore <dgilmore@redhat.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ARM: orion5x: fix use of callee-saved registers in lowloevel_initMans Rullgard2018-06-071-84/+84
| | | | | | | | | The lowlevel_init function uses r4 and r6 without preserving their values as required by the AAPCS. Use r0 and r2 instead as these are call-clobbered. Signed-off-by: Mans Rullgard <mans@mansr.com> Reviewed-by: Chris Packham <judge.packham@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2018-06-061-27/+2
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| * ARM: dts: exynos5: add the interrupt-parent propertyJaehoon Chung2018-05-161-0/+2
| | | | | | | | | | | | | | | | Add the interrupt-parent property as gic. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * ARM: dts: exynos5: remove the duplicated nodesJaehoon Chung2018-05-161-27/+0
| | | | | | | | | | | | | | | | Remove the duplicated gic and combiner nodes in exynos5.dtsi. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | mach-stm32: Enable SPL_RESET_SUPPORT flagPatrice Chotard2018-06-051-0/+1
| | | | | | | | | | | | | | | | | | Since commit 0e373c0ade8c ("spl: add SPL_RESET_SUPPORT"), reset is supported in SPL, enable this flag for STM32F SoCs family. This allows to remove a specific case in RCC mfd driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | ARM: add SBx81LIFKW boardChris Packham2018-06-052-0/+137
| | | | | | | | | | | | | | | | | | | | This is a series of line cards for Allied Telesis's SBx8100 chassis switch. The CPU block is common to the SBx81GS24a, SBx81XS6, SBx81XS16 and SBx81GT40 cards collectively referred to as SBx81LIFKW in u-boot. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | ARM: kirkwood: remove automatic I2C config if DM_I2C is enabledChris Packham2018-06-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The mach/config.h file would helpfully define CONFIG_SYS_I2C and CONFIG_SYS_I2C_MVTWSI if CONFIG_CMD_I2C was defined by the board. This conflicts with the way DM_I2C works. As a transitional measure don't automatically define these if CONFIG_DM_I2C is defined. It should be possible to remove this once all kirkwood boards are migrated to DM. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm: kirkwood: lsxl: Add SPI driver model supportMichael Walle2018-06-052-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch shows how to enable driver model support for the LS-CHLv2 and LS-XHL boards. There are a couple of open questions: - do I need the u-boot,dm-pre-reloc tags in the device tree? - should mach/config.h define CONFIG_DM_SEQ_ALIAS? - how can we split this patch or are there any other pending patches which does the same and I didn't catch these. This patch is based on the http://git.denx.de/u-boot-marvell.git (master branch) and needs the following patches, which are still pending: https://patchwork.ozlabs.org/patch/909618/ https://patchwork.ozlabs.org/patch/909617/ https://patchwork.ozlabs.org/patch/909973/ Signed-off-by: Michael Walle <michael@walle.cc> Tested-by: Michael Walle <michael@walle.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm: mvebu: switch clearfog to use device-tree i2c and gpioJon Nettleton2018-06-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This switches the clearfog boards to use DM based gpio and i2c drivers. The io expanders are configured via their device-tree entries. Signed-off-by: Jon Nettleton <jon@solid-run.com> [baruch: add DT i2c aliases] Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | mvebu: a38x: Force receiver detected on PCIe lanesRabeeh Khoury2018-06-052-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some QCA988x based modules presence is not detected by the SERDES lanes, so force this detection which will trigger the LTSSM state machine to negotiate link. An example of such a card is WLE900VX. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Tested-by: Chris Packham <judge.packham@gmail.com> Tested-by: Mario Six <mario.six@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* | db410c: Added pre-relocation attribute to pinctrlRamon Fried2018-06-041-0/+8
| | | | | | | | | | | | | | | | u-boot,dm-pre-reloc was missing from pinctrl and it's children node. causing failure to configure pin mux before relocation. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2018-06-0414-474/+228
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| * | board: sun50i: Add Amarula A64-Relic initial supportJagan Teki2018-06-042-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Amarula A64-Relic is A64 based IoT device, which support - Allwinner A64 Cortex-A53 - Mali-400MP2 GPU - AXP803 PMIC - 1GB DDR3 RAM - 8GB eMMC - AP6330 Wifi/BLE - MIPI-DSI - CSI: OV5640 sensor - USB OTG - 12V DC power supply Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * | arm64: allwinner: h5: orangepi-prime: Sync usb otg nodes from LinuxJagan Teki2018-05-281-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | orangepi-prime has usb otg routed host with either EHCI0/OHCI0 sync the same from Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
| * | arm64: allwinner: h5: orangepi-pc2: Sync usb otg nodes from LinuxJagan Teki2018-05-281-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | orangepi-pc2 has usb otg routed host with either EHCI0/OHCI0 sync the same from Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
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