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* Merge tag 'u-boot-rockchip-20201031' of ↵WIP/30Oct2020Tom Rini2020-10-3011-11/+366
|\ | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - New PX30 board: Engicam PX30.Core; - Fix USB HID support for rock960; - Remove host endianness dependency for rockchip mkimage; - dts update for rk3288-tinker; - Enable console MUX for some ROCKPi boards; - Add config-based ddr selection for px30;
| * rockchip: Add Engicam PX30.Core C.TOUCH 2.0Jagan Teki2020-10-303-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * arm64: dts: rockchip: px30: Add Engicam C.TOUCH 2.0Jagan Teki2020-10-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose carrier board with capacitive touch interface. Genaral features: - TFT 10.1" industrial, 1280x800 LVDS display - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector SOM's like PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * rockchip: Add Engicam PX30.Core EDIMM2.2 Starter KitJagan Teki2020-10-303-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board from Engicam. PX30.Core needs to mount on top of this Evaluation board for creating complete PX30.Core EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * rockchip: px30: Add EVB_PX30 Kconfig helpJagan Teki2020-10-301-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | TARGET_EVB_PX30 can be possible to use other px30 boards. Add the help text for existing EVB, so-that the new boards which are resuing this config option can mention their board help text. This would help to track which boards are using EVB_PX30 config. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: Add Engicam PX30.Core SOMMichael Trimarchi2020-10-301-0/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. General features: - Rockchip PX30 - Up to 2GB DDR4 - eMMC 4 GB expandible - rest of PX30 features PX30.Core needs to mount on top of Engicam baseboards for creating complete platform boards. Possible baseboards are, - EDIMM2.2 - C.TOUCH 2.0 Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter KitJagan Teki2020-10-302-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board. Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Mini PCIe - MIPI CSI - 2x CAN - Audio Out SOM's like PX30.Core needs to mount on top of this Evaluation board for creating complete PX30.Core EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: Add chosen node for ROCK-Pi N8Jagan Teki2020-10-301-0/+6
| | | | | | | | | | | | | | | | | | Add chosen node in -u-boot.dtsi for ROCK-Pi N8 board. This will help to get serial out messages. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * rockchip: dts: tinker: remove unnecessary nodeStefan Agner2020-10-301-4/+0
| | | | | | | | | | | | | | | | The property reg-shift with the same value is present in the base device tree already. Remove unnecessary node from rk3288-tinker.dts. Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: dts: tinker: move i2c node to shared device treeStefan Agner2020-10-302-7/+7
| | | | | | | | | | | | | | | | | | The I2C EEPROM is present on Tinker Board S as well. Move the i2c node to the shared, U-Boot specific rk3288-tinker-u-boot.dtsi device tree. Cc: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | Merge tag 'dm-pull-30oct20' of ↵Tom Rini2020-10-309-18/+56
|\ \ | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-dm of-platdata and dtoc improvements sandbox SPL tests binman support for compressed sections
| * | imx: mx6cuboxi: Disable thermal driver in SPLSimon Glass2020-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This feature is incompatble with of-platdata since it uses the U_BOOT_DEVICE() macro. With of-platdata the only devices permitted are those created by dtoc. The driver is not used in SPL anyway, so exclude it from that build. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Fabio Estevam <festevam@gmail.com>
| * | x86: apl: Take advantage of the of-platdata parent supportSimon Glass2020-10-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Now that parent devices are supported with of-platadata, we don't need the messy code to fix up the parent pointers and allocations on Apollo Lake. Put the code behind a condition. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: apl: Enable SPI flash in TPL with APL_SPI_FLASH_BOOTSimon Glass2020-10-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | At present, enabling CONFIG_APL_SPI_FLASH_BOOT does not build since SPI and SPI flash are not enabled for TPL. Add a condition to fix this and tidy up a build warning in the SPI-flash driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: Add a test for of-platdata parent informationSimon Glass2020-10-292-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add a simple test that we can obtain the correct parent for an I2C device. This requires updating the driver names to match the compatible strings, adding them to the devicetree and enabling a few options. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: test: Add a test for of-platdata phandlesSimon Glass2020-10-291-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | We have a test in dtoc for this feature, but not one in U-Boot itself. Add a simple test that checks that the information comes through correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: test: Drop of-platdata pytestSimon Glass2020-10-293-22/+0
| | | | | | | | | | | | | | | | | | Now that we have a C version of this test, drop the Python implementation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | sandbox: Allow selection of SPL unit testsSimon Glass2020-10-293-1/+11
| | | | | | | | | | | | | | | | | | Now that we have more than one test, add a way to select the test to run. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: test: Add a way to run SPL testsSimon Glass2020-10-293-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a -u flag for U-Boot SPL which requests that unit tests be run. To make this work, export dm_test_main() and update it to skip test features that are not used with of-platdata. To run the tests: $ spl/u-boot-spl -u U-Boot SPL 2020.10-rc5 (Oct 01 2020 - 07:35:39 -0600) Running 0 driver model tests Failures: 0 At present there are no SPL unit tests. Note that there is one wrinkle with these tests. SPL has limited memory available for allocation. Also malloc_simple does not free memory (free() is a nop) and running tests repeatedly causes driver-model to reinit multiple times and allocate memory. Therefore it is not possible to run more than a few tests at a time. One solution is to increase the amount of malloc space in sandbox_spl. This is not a problem for pytest, since it runs each test individually, so for now this is left as is. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | sandbox: make SDL window resizableHeinrich Schuchardt2020-10-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without resizing the SDL window showed by ./u-boot -D -l is not legible on a high resolution screen. Allow resizing the window Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellWIP/29Oct2020Tom Rini2020-10-292-6/+25
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | - Armada 8k: Add NAND support via PXA3xx NAND driver (Baruch) - Armada 8k: Use ATF serdes init instead of the "old" U-Boot version (Baruch) - Minor update to Octeon TX/TX2 defconfig (Stefan)
| * | | arm: dts: armada-cp110-master: update nand-controllerBaruch Siach2020-10-291-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align node properties to kernel dts node. The change of compatible property does not affect any currently supported board. Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility with the current driver. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
| * | | arm: dts: armada-cp110-slave: add missing cps_nandShmuel Hazan2020-10-291-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align node properties to kernel dts node. Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility with the current driver. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
* | | | Merge tag 'xilinx-for-v2021.01-v2' of ↵Tom Rini2020-10-2912-240/+272
|\ \ \ \ | |_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.01-v2 common: - Add support for 64bit loadables from SPL xilinx: - Update documentation and record ownership - Enable eeprom board detection based legacy and fru formats - Add support for FRU format microblaze: - Optimize low level ASM code - Enable SPI/I2C - Enable distro boot zynq: - Add support for Zturn V5 zynqmp: - Improve silicon detection code - Enable several kconfig options - Align DT with the latest state - Enabling security commands - Enable and support FPGA loading from SPL - Optimize xilinx_pm_request() calling versal: - Some DTs/Kconfig/defconfig alignments - Add binding header for clock and power zynq-sdhci: - Add support for tap delay programming zynq-spi/zynq-qspi: - Use clock framework for getting clocks xilinx-spi: - Fix some code issues (unused variables) serial: - Check return value from clock functions in pl01x
| * | | xilinx: Consolidate board_fit_config_name_match() for Xilinx platformsMichal Simek2020-10-292-24/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move board_fit_config_name_match() from Zynq/ZynqMP to common location. This change will open a way to use it also by Microblaze and Versal. Through this function there is a way to handle images with multiple DTBs. For now match it with DEVICE_TREE as is done for Zynq. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | xilinx: Merge together BOOT_SCRIPT_OFFSET between MB and ARMMichal Simek2020-10-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | There is no reason not to use commong Kconfig by Microblaze too. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | arm64: zynqmp: Fix zynqmp mini qspi max frequencyT Karthik Reddy2020-10-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For zynqmp qspi, frequencies up to 40MHz will work irrespective of feedback clock enabled or disabled. If we want higher than 40Mhz the feedback clock should be enabled. With spi-max-frequency 108MHz it is not working when the feedback clock is disabled. Change it to 40MHz so that it works irrespective of feedback clock enabled or disabled. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | arm64: zynqmp: Add support for SHA3 commandT Karthik Reddy2020-10-271-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for SHA3 command. It takes data blob as input and generates 48 bytes sha3 hash value. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | arm64: zynqmp: Add support for RSA commandT Karthik Reddy2020-10-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for RSA command, performs RSA encrypt & RSA decrypt on data blob of key size. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | arm64: zynqmp: Add support for encryption and decryption on data blobSiva Durga Prasad Paladugu2020-10-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for encryption and decryption on a given data blob using different key sources such as userkey(KUP), device key and PUF key. Inorder to support this a new zynqmp command(zynqmp aes) has been introduced. Command: zynqmp aes srcaddr ivaddr len aesop keysrc dstaddr [keyaddr]\n" Encrypts or decrypts blob of data at src address and puts it\n" back to dstaddr using key and iv at keyaddr and ivaddr\n" respectively. keysrc values specifies from which source key\n" has to be used, it can be User/Device/PUF key. A value of 0\n" for KUP(user key),1 for DeviceKey and 2 for PUF key. The\n" aesop value would specify the operationwhich can be 0 for\n" decrypt and 1 for encrypt(1) operation\n"; Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | arm64: versal: Update mini u-boot eMMC node parametersAshok Reddy Soma2020-10-272-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mini u-boot eMMC dt parameters are not in sync with full u-boot dt. Frequency for eMMC is fixed to 25Mhz. Due to this, mmc multi-block write commands are failing. Increase frequency to 200Mhz to fix this issue. Add bus-width = <8>, non-removable and disable-wp properties to the node as this is eMMC. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Enable spi for microblazeT Karthik Reddy2020-10-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPI drivers and driver model for microblaze. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: Add Z-turn board V5Alexandre GRIVEAUX2020-10-274-108/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding Z-turn board V5 to resolve the change between: "Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035 "Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel KSZ9031 At this time the S25FL128SAGNFI003 doesn't work because of bug: *** Warning - spi_flash_probe_bus_cs() failed, using default environment zynq-zturn was checked on V5 board, same error. Maybe Z-turn board have the same problem (board with W25Q128BVFIG). Signed-off-by: Alexandre GRIVEAUX <agriveaux@deutnet.info> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: start.S: Use board_init_f_alloc/init in early initOvidiu Panait2020-10-271-24/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement early init by calling generic board_init_f_alloc_reserve and board_init_f_init_reserve functions: * drop SYS_MALLOC_F_LEN related code, as allocation and gd->malloc_base assignment are taken care of by the generic functions * drop _gd logic Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
| * | | microblaze: start.S: Factor out exception setup code to __setup_exceptionsOvidiu Panait2020-10-271-94/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the exceptions setup code is duplicated in pre-relocation and post-relocation init. Factor out this code to __setup_exceptions asm routine to get rid of the duplication. __setup_exceptions is called with a relocation offset parameter (r5) which is set to zero for pre-reloc init and gd->reloc_off for post-reloc exception setup. Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2020-10-2912-10/+521
|\ \ \ \ | |_|/ / |/| | | | | | | | | | | | | | | - Bug fixes and updates on vid, ls1088a lx2160a and other layerscape platforms. - Add optee_rpmb support for LX2 & Kontron sl28 support
| * | | armv8: layerscape: don't remove crypto node if just partially disabledMichael Walle2020-10-231-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On all newer Layerscape SoCs, only the export-controlled ciphers of the crypto module are disabled on non-E parts. Thus it doesn't make sense to completely remove the node. Linux will figure out what is there and what is not. Just remove it for older SoCs, where the module is indeed completely disabled on non-E parts. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | board: kontron: add sl28 supportMichael Walle2020-10-238-0/+405
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic support for the Kontron SMARC-sAL28 board. This includes just the bare minimum to be able to bring up the board and boot linux. For now, the Single and Dual PHY variant is supported. Other variants will fall back to the basic variant. In particular, there is no watchdog support for now. This means that you have to disable the default watchdog, otherwise you'll end up in the recovery bootloader. See the board README for details. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | net: lx2160a.c: Update to set ECx_PMUX precedenceRazvan Ionut Cirjan2020-10-232-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | pci: layerscape: add a way of specifying additional iommu mappingsLaurentiu Tudor2020-10-231-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add an u-boot env var and a device tree property (to be used for example in more static scenarios such as hardwired PCI endpoints that get initialized later in the system setup) that would allow two things: - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number of VFs that will ever be created for it - for hot-plug case, specify the B.D.F with which the device will show up on the PCI bus More details can be found in the included documentation: arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | | | test: Add tests for the multiplexer frameworkJean-Jacques Hiblot2020-10-281-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide tests to check the behavior of the multiplexer framework. Two sets of tests are added. One is using an emulated multiplexer driver that can be used to test basic functionality like select, deselect, etc. The other is using the mmio mux which adds tests specific to it. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | riscv: fu540: dts: Correct reg size of clint nodePragnesh Patel2020-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
* | | | riscv: Move timer portions of SiFive CLINT to drivers/timerSean Anderson2020-10-261-39/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
* | | | timer: Add _TIMER suffix to Andes PLMT KconfigSean Anderson2020-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
* | | | riscv: Move Andes PLMT driver to drivers/timerSean Anderson2020-10-263-58/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
* | | | riscv: k210: Reduce DMA block sizeSean Anderson2020-10-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although the max DMA size supported by the hardware register is 22 bits (or 4M), the Linux driver for this device only supports transfers of up to 2M. On a device with 8M total memory, I don't think it will make too much of a difference. Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
* | | | riscv: Only enable OF_BOARD_FIXUP for S-ModeSean Anderson2020-10-261-1/+1
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is unsafe to enable OF_BOARD_FIXUP only based on OF_SEPARATE. OF_SEPARATE may indicate that the user wishes U-Boot to use a different device tree than one obtained via OF_PRIOR_STAGE. However, OF_SEPARATE may also indicate that the device tree which would be obtained via OF_PRIOR_STAGE is invalid, nonexistant, or otherwise unusable. In this latter case, enabling OF_BOARD_FIXUP will result in corruption of the device tree. To remedy this, only enable OF_BOARD_FIXUP if U-Boot is configured for S-Mode. Fixes: 1c17e55594a394ced7de88d91be294eaf8c564c1 Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Liang <ycliang@andestech.com>
* | | Revert "arch: arm/xen: add putc() for debugging"Tom Rini2020-10-231-6/+0
| | | | | | | | | | | | | | | | | | This reverts commit 3a51b2a2c3cedc0d2a9ce981b8e00ab8cefcb6b7. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiWIP/22Oct2020Tom Rini2020-10-223-15/+120
|\ \ \ | |/ / |/| | | | | | | | - sun8i emac changes (Andre) - SCP firmware (Samuel)
| * | sunxi: binman: Add support for including SCP firmwareSamuel Holland2020-10-221-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner sun50i SoCs contain an OpenRISC 1000 CPU that functions as a System Control Processor, or SCP. ARM Trusted Firmware (ATF) communicates with the SCP over SCPI to implement the PSCI system suspend, shutdown and reset functionality. Currently, SCP firmware is optional; the system will boot and run without it, but system suspend will be unavailable. Since all communication with the SCP is mediated by ATF, the only thing U-Boot needs to do is load the firmware into SRAM. The SCP firmware occupies the last 16KiB of SRAM A2, immediately following ATF. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
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