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* ARM: dts: k2g-evm: enable USB0 and USB1Jean-Jacques Hiblot2018-12-142-0/+84
| | | | | Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: am335x-pdu001: Move from embedded to separate DTBFelix Brack2018-12-121-0/+1
| | | | | | | There is no need for an embedded device tree for this board so let the build process generate a separate u-boot.dtb file instead. Signed-off-by: Felix Brack <fb@ltec.ch>
* Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2018-12-1028-326/+1586
|\ | | | | | | | | | | | | | | Add TFA boot flow for some Layerscape platforms Add support for lx2160a SoC [trini: Add a bunch of missing MAINTAINERS entries] Signed-off-by: Tom Rini <trini@konsulko.com>
| * armv8: lx2160a: Add LX2160A SoC SupportPriyanka Jain2018-12-0613-9/+534
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8:fsl-layerscape: Add support for Chassis 3.2Priyanka Jain2018-12-065-5/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: lsch3: Add support of serdes3 modulePriyanka Jain2018-12-063-0/+76
| | | | | | | | | | | | | | | | | | Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: dts: fsl-ls2080a: add sata node supportPeng Ma2018-12-063-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | One ls2080a, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Add sata node to support this feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: dts: fsl-ls1088a: add sata node supportPeng Ma2018-12-063-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | One ls1088a, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Add sata node to support this feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: dts: fsl-ls1046a: add sata node supportPeng Ma2018-12-063-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | One ls1046a, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Add sata node to support this feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: add support of MC framework for TFAPankit Garg2018-12-061-1/+52
| | | | | | | | | | | | | | | | | | Add support of MC framework for TFA Make MC framework independent of boot source. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: sec_firmware: return job ring status as true in TFABOOTPankit Garg2018-12-061-0/+4
| | | | | | | | | | | | | | | | | | Returns job ring status as true in TFABOOT, as one job ring is always reserved. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: sec_firmware: change el2_to_aarch32 SMC IDRajesh Bhagat2018-12-061-1/+1
| | | | | | | | | | | | | | | | Changes the el2_to_aarch32 SMC ID from 0xc000ff04 to 0xc200ff17, it is applicable to both TFA and non-TFA boot. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Update parsing boot sourceYork Sun2018-12-062-4/+23
| | | | | | | | | | | | | | | | | | | | | | Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com>
| * armv8: layerscape: skip OCRAM init for TFABOOTRajesh Bhagat2018-12-061-1/+2
| | | | | | | | | | | | | | | | OCRAM initialization is performed by TFA, Hence skipped from u-boot. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: layerscape: add SMC calls for DDR size and bank infoRajesh Bhagat2018-12-062-0/+88
| | | | | | | | | | | | | | | | Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: bootcmd identification for TFABOOTPankit Garg2018-12-062-0/+91
| | | | | | | | | | | | | | | | | | | | Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: layerscape: remove EL3 specific erratas for TFABOOTRajesh Bhagat2018-12-061-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | Removes EL3 specific erratas for TFABOOT, And now taken care in TFA. ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511, SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, SYS_FSL_ERRATUM_A009803, SYS_FSL_ERRATUM_A009942, SYS_FSL_ERRATUM_A010165 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: identify boot source from PORSR registerRajesh Bhagat2018-12-064-0/+275
| | | | | | | | | | | | | | | | | | | | | | | | PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: layerscape: Add TFABOOT supportRajesh Bhagat2018-12-062-3/+13
| | | | | | | | | | | | | | | | Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3Pankit Garg2018-12-061-1/+4
| | | | | | | | | | | | | | | | | | Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: layerscape: Enable routing SError exceptionYork Sun2018-12-061-0/+9
| | | | | | | | | | | | | | | | In case SError happens at EL2, if SCR_EL3[EA] is not routing it to EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes the exception to EL2. Otherwise this exception is not taken. Signed-off-by: York Sun <york.sun@nxp.com>
| * move data structure out of cpu.hYork Sun2018-12-042-300/+297
| | | | | | | | | | | | | | Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
* | Merge tag 'mips-fixes-for-2019.01' of git://git.denx.de/u-boot-mipsTom Rini2018-12-102-12/+0
|\ \ | | | | | | | | | | | | | | | - mips: bcm: disable CONFIG_SWAP_IO_SPACE to force native endianess in readl() & co. this fixes 09ace9161b95ad3a04b33d1d6a65a929901d28c8 - mips: bcm6838: fix device tree warning
| * | bmips: bcm6838: fix device tree warningÁlvaro Fernández Rojas2018-12-101-2/+0
| | | | | | | | | | | | Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
| * | bmips: swapping IO space isn't requiredÁlvaro Fernández Rojas2018-12-101-10/+0
| | | | | | | | | | | | | | | Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | Merge tag 'for-master-20181210' of git://git.denx.de/u-boot-rockchipTom Rini2018-12-101-2/+4
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improvements: - init DRAM for RK322x in SPL - add FAN53555 PMIC/regulator driver - update MicroCrystal RV3029 driver to Kconfig and sync from Linux - add bootcount uclass and first DM-driver for bootcount
| * | | rockchip: rk3399-puma: enable fan53555 regulators in DTSPhilipp Tomsich2018-12-101-2/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | Now that we have FAN53555 support, we can enable the regulators in our DTS. To make these easier to identify on the U-Boot commandline, we rename them to the names of the voltage rails they control. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2018-12-1012-198/+130
|\ \ \ | | | | | | | | | | | | | | | | - DM_I2C_COMPAT removal for all ti platforms from Jean-Jacques Hiblot - Fix in i2c command help output from Chirstoph Muellner.
| * | | dra7: Allow selecting a new dtb after board detection.Jean-Jacques Hiblot2018-12-101-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DRA7 platforms requires that the dtb used in the SPL really matches the platform to have the best MMC performances. To detect the board type/version an I2C EEPROM is read. This requires that DM is initialized before the detection. As a consequence we must reset the DM after the board detection is a new dtb would better match the platform. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | | ti: remove usage of DM_I2C_COMPAT and don't disable DM_I2C in SPLJean-Jacques Hiblot2018-12-103-11/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C API when DM_I2C is used. The goal is to eventually remove DM_I2C_COMPAT when all I2C "clients" have been migrated to use the DM API. This a step in that direction for the TI based platforms. Build tested with buildman: buildman -dle am33xx ti omap3 omap4 omap5 davinci keystone boot tested with: am335x_evm, am335x_boneblack, am335x_boneblack_vboot (DM version), am57xx_evm, dra7xx_evm, k2g_evm, am437x_evm Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | | omap: detect the board after DM is availableJean-Jacques Hiblot2018-12-102-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to use DM_I2C, we need to move the board detection after the early SPL initialization. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | | dts: am43x: omap5: Add node for I2C in SPLJean-Jacques Hiblot2018-12-102-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | | am335x: Register the I2C controllers if DM_I2C is used.Jean-Jacques Hiblot2018-12-101-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If DM_I2C is used , the I2C controllers must be registered as U_BOOT_DEVICE because OF_CONTROL is not used in the SPL. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | | i2c: omap24xx_i2c: Use platdata to probe the deviceJean-Jacques Hiblot2018-12-102-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the driver to be used without OF_CONTROL. AM335x support DM_SPL but does not use SPL_OF_CONTROL. Enabling DM_I2C in SPL thus requires that the omap I2C can be passed platdata. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * | | i2c: omap24xx_i2c: Move away from SoC specific headers for reg offsetVignesh R2018-12-104-182/+0
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move away from SoC specific headers to handle different register layout. Instead use driver data to get appropriate register layouts like in the kernel. While at it, perform some mostly cosmetic alignment/cleanup in the functions being updated. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2018-12-102-6/+22
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| * | | ARM: rmobile: Fix to enable icache early in Gen3Takeshi Kihara2018-12-072-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the problem that u-boot will not start unless icache is enabled early. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * | | ARM: rcar_gen3: fix protection area access errorTakeshi Kihara2018-12-071-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the problem that "main memory domain AXI secure access protection error" occurs. Exclude the area (0x43f00000 to 0x47DFFFFF) set by DBSC from the map area. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
| * | | ARM: rcar_gen3: fix protection area access error at Cortex-A53Hiroyuki Yokoyama2018-12-071-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the problem that "main memory domain AXI secure access protection error" occurs when booting Cortex-A53. Exclude the area (0x43f00000 to 0x47DFFFFF) set by DBSC from the map area. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2018-12-101-4/+4
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| * | | | arm: socfpga: imply SPL options instead of selectSimon Goldschmidt2018-12-071-4/+4
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For a small SPL, it should be possible to build without SPI(-flash) drivers or wihout MMC drivers. For this to work, we have to change from 'select'ing options to 'imply'ing them. With this change, I can have SPL trimmed to my hard-wired starting method (SPI-NOR or MMC) while still including all drivers in U-Boot. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2018-12-103-2/+10
|\ \ \ \ | | | | | | | | | | | | | | | - DWC3 and UDC cleanup
| * | | | dts: dra7x: make ocp2scp@4a080000 compatible with simple-busJean-Jacques Hiblot2018-12-071-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is required when DM_USB is used, to bind the USB phys. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | | | syscon: dm: Add a new method to get a regmap from DTSJean-Jacques Hiblot2018-12-071-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | syscon_regmap_lookup_by_phandle() can be used to get the regmap of a syscon device from a reference in the DTS. It operates similarly to the linux version of the namesake function. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | usb: introduce a separate config option for DM USB deviceJean-Jacques Hiblot2018-12-071-0/+2
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using CONFIG_DM_USB for this purpose prevents using DM_USB for host and not for device. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* | | | efi: payload: only init usb if necessaryBin Meng2018-12-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up until now the call to initialize the USB subsystem was hardcoded for U-Boot running as an EFI payload. This was used to enable the use of a USB keyboard in the U-Boot shell. However not all boards might need this functionality. As initializing the USB subsystem can take a considerable amount of time (several seconds on some boards), we now initialize the USB subsystem only if U-Boot is configured to use USB keyboards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
* | | | coreboot: only init usb if necessaryThomas RIENOESSL2018-12-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up until now the call to initialize the USB subsystem was hardcoded for U-Boot running as a coreboot payload. This was used to enable the use of a USB keyboard in the U-Boot shell. However not all boards might need this functionality. As initializing the USB subsystem can take a considerable amount of time (several seconds on some boards), we now initialize the USB subsystem only if U-Boot is configured to use USB keyboards. Signed-off-by: Thomas RIENOESSL <thomas.rienoessl@bachmann.info> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
* | | | x86: kconfig: Allow board defconfig file to disable 8259 and APICBin Meng2018-12-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the Kconfig options (CONFIG_I8259_PIC and CONFIG_APIC) do not include a prompt message, which makes it impossible to be disabled from a board defconfig file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | x86: Wrap calls to 8259 with CONFIG_I8259_PICBin Meng2018-12-101-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mask_irq(), unmask_irq() and specific_eoi() are provided by the i8259 PIC driver and should be wrapped with CONFIG_I8259_PIC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
* | | | x86: make the LAPIC / IOAPIC construct switchable with KconfigHannes Schmelzer2018-12-103-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are still systems running which do not have any LAPIC or even IOAPIC. Responsible MSRs for those do not exist and the systems are crashing on trying to setup LAPIC. This commit makes the APIC stuff able to switch off for those boards which dont' have an LAPIC / IOAPIC. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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