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* armv7: ls1021a: Drop macro CONFIG_LS102XAYork Sun2017-04-174-4/+4
| | | | | | Use CONFIG_ARCH_LS1021A instead. Signed-off-by: York Sun <york.sun@nxp.com>
* armv8: ls1043a: Drop macro CONFIG_LS1043AYork Sun2017-04-173-3/+3
| | | | | | Use CONFIG_ARCH_LS1043A instead. Signed-off-by: York Sun <york.sun@nxp.com>
* armv8: ls2080a: Drop macro CONFIG_LS2080AYork Sun2017-04-178-10/+10
| | | | | | Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com>
* arm: ls1046ardb: Add SD secure boot targetRuchika Gupta2017-04-171-1/+1
| | | | | | | | | | | | | | | | | | | | - Add SD secure boot target for ls1046ardb. - Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. - CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM (128K) where 32K are reserved for use by boot ROM and 6K for the header. - Reduce the size of CAAM driver for SPL Blobification functions and descriptors, that are not required at the time of SPL are disabled. Further error code conversion to strings is disabled for SPL build. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: ls1043ardb: Add NAND secure boot targetRuchika Gupta2017-04-171-1/+6
| | | | | | | | | | | | | | | | | Add NAND secure boot target for ls1043ardb. - Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. - MACRO for CONFIG_BOOTSCRIPT_COPY_RAM is enabled to copy Bootscript from NAND to DDR. Offsets for Bootscript on NAND and DDR have been also defined. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: ls1043ardb: Add SD secure boot targetRuchika Gupta2017-04-172-2/+25
| | | | | | | | | | | | | | | | | | | | - Add SD secure boot target for ls1043ardb. - Implement FSL_LSCH2 specific spl_board_init() to setup CAAM stream ID and corresponding stream ID in SMMU. - Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. - CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM (128K) where 32K are reserved for use by boot ROM and 6K for secure boto header. - Error messages during SPL boot are limited to error code numbers instead of strings to reduce the size of SPL image. Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: SECURE_BOOT: Enable chain of trust on LS1012A platformVinitha Pillai-B572232017-04-173-1/+10
| | | | | | | | | Define bootscript and its header addresses for QSPI target Also add PPA header address in Kconfig Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: SECURE_BOOT: Enable chain of trust on LS1046A platformVinitha Pillai-B572232017-04-173-5/+16
| | | | | | | | Define bootscript and its header addresses for QSPI target. Also define PPA header address to enable PPA validation. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
* armv8: fsl-layerscape: SECURE BOOT: Add header address of PPA in kconfigVinitha Pillai-B572232017-04-173-13/+15
| | | | | | | | The header address of PPA defined in Kconfig. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc: T1042RDB: SECURE BOOT: Remove CONFIG_CMD_BLOB from SPL compilationVINITHA PILLAI2017-04-171-1/+1
| | | | | | | | BLOB feature is not required during SPL compilation. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2017-04-145-1/+51
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| * board: toradex: colibri_vf: Add DCU support for Colibri VybridStefan Agner2017-04-144-0/+50
| | | | | | | | | | | | | | | | | | | | | | The Vybrid SoC family has the same display controller unit (DCU) like the LS1021A SoC. This patch adds platform data, pinmux defines and clock control to enable the driver for Toradex Colibri Vybrid module. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * Convert CONFIG_FSL_DCU_FB to KconfigSanchayan Maity2017-04-141-1/+1
| | | | | | | | | | | | | | | | | | Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and convert it to Kconfig. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Reviewed-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Alison Wang <alison.wang@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2017-04-144-20/+26
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| * | arm: socfpga: Convert Altera DDR SDRAM driver to use KconfigLey Foon Tan2017-04-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert Altera DDR SDRAM driver to use Kconfig method. Enable ALTERA_SDRAM by default if it is on Gen5 target. Arria 10 will have different driver. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: Disable OC on MCVEVKMarek Vasut2017-04-141-0/+1
| | | | | | | | | | | | | | | | | | | | | Disable the OC test on MCVEVK as the old PHY version does not provide this information. This fixes the USB OTG operation. Signed-off-by: Marek Vasut <marex@denx.de>
| * | ARM: socfpga: Rename MCVEVKMarek Vasut2017-04-142-6/+6
| | | | | | | | | | | | | | | | | | The board is now manufactured by Aries Embedded GmbH , rename it. Signed-off-by: Marek Vasut <marex@denx.de>
| * | ARM: socfpga: boot0 hook: remove macro from boot0 header fileChee, Tien Fong2017-04-141-14/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole header file") miss out cleaning macro in this header file, and this has broken implementation of a boot header capability in socfpga SPL. Remove the macro in this file, and recovering it back to proper functioning. Fixes: ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole header file") Signed-off-by: Chee, Tien Fong <tien.fong.chee@intel.com>
| * | ARM: socfpga: cyclone5-socdk: Enable ports A & CGeorges Savoundararadj2017-04-141-0/+8
| |/ | | | | | | | | | | | | | | | | | | | | With the port C enabled, we can read the GPI input state of: * the DIP switches (USER_DIPSW_HPS[3:0]/HPS_GPI[7:4]) * the push buttons (USER_PB_HPS[3:0]/HPS_GPI[11:8]) Signed-off-by: Georges Savoundararadj <savoundg@gmail.com> Signed-off by: Sid-Ali Teir <git.syedelec@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Marek Vasut <marex@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2017-04-144-275/+1126
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| * | mmc: meson: add MMC driver for Meson GX (S905)Carlo Caione2017-04-141-0/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver implements MMC support on Meson GX (S905) based systems. It's based on Carlo Caione's work, changes: - BLK support added - general refactoring Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Tested-by: Vagrant Cascadian <vagrant@debian.org>
| * | arm: dts: update Meson GXBB / Odroid-C2 DT with recent Linux versionHeiner Kallweit2017-04-143-275/+1037
| |/ | | | | | | | | | | | | | | | | | | | | As a prerequisite for adding a Meson GX MMC driver update the Meson GXBB / Odroid-C2 device tree in Uboot with the latest version from Linux. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2017-04-1340-223/+6543
|\ \ | | | | | | | | | | | | Here with some DM changes as well as the long-standing AT91 DM/DT conversion patches which I have picked up via dm.
| * | ARM: at91: lds: use "_image_binary_end" for DT locationWenyou Yang2017-04-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The MMC SPL locates the BSS section to a different memory region from text, then use "_image_binary_end" variable to point to the correct device tree location. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | ARM: spl: atmel: move mem_init() advance in SPL init.Wenyou Yang2017-04-131-1/+2
| | | | | | | | | | | | | | | | | | | | | Because the MMC SPL puts the bbs section in the ddr memory, move calling mem_init() before calling spl_init(). Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | ARM: spl: atmel: bring in serial device before initWenyou Yang2017-04-131-0/+8
| | | | | | | | | | | | | | | | | | | | | Before setting up the serial communications, bring in the serial device from the device tree file. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | ARM: at91: spl: specify MMC and NAND boot deviceWenyou Yang2017-04-131-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When OF_CONTROL is enabled, MMC boot device should not be detected automatically, it should be MMC1 fixedly only the status "enabled" is available. Add NAND Flash boot device as well. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | ARM: dts: at91: add dts file for sama5d4ekWenyou Yang2017-04-132-0/+344
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree file for sama5d4ek board. The dts file is copied from Linux-4.4, do the following changes. - add the "u-boot,dm-pre-reloc" property to determine which nodes which are needed by SPL and by the board_init_f stage. - fix the compilation warning. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | ARM: dts: at91: add dts files for sama5d4 XplainedWenyou Yang2017-04-133-0/+2224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree files for sama5d4 Xplained board. The dts files are copied from Linux-4.4, do the following changes. - add reg property for pinctrl node. - move the gpio nodes(pioA, pioB, pioC ...) from the pinctrl child's nodes to its slibling nodes. - add the "u-boot,dm-pre-reloc" property to determine which nodes which are needed by SPL and by the board_init_f stage. - fix the compilation warnings. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | ARM: at91: dt: add dts file for sama5d3 XplainedWenyou Yang2017-04-132-0/+351
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree file for sama5d3 Xplained board. The dts files are copied from the Linux-4.9, do changes as below. - add the "u-boot,dm-pre-reloc" property to determine which nodes which are needed by SPL and by the board_init_f stage. - fix the compile warning. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | ARM: at91: dt: add dts files for sama5d3xek boardWenyou Yang2017-04-1325-0/+3382
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree files for sama5d3xek board. The dts files are copied from Linux-4.9, do the changes as below. - add reg property for the pinctrl node. - move the gpio nodes (pioA, pioB, pioC ...) as the pinctrl's slibling nodes. - add the "u-boot,dm-pre-reloc" property to determine which nodes which are needed by SPL and by the board_init_f stage. - fix the compile warning. - add spi0 node aliases. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | pinctrl: at91: add pinctrl driverWenyou Yang2017-04-131-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AT91 PIO controller is a combined gpio-controller, pin-mux and pin-config module. The peripheral's pins are assigned through per-pin based muxing logic. Each SoC will have to describe the its limitation and pin configuration via device tree. This will allow to do not need to touch the C code when adding new SoC if the IP version is supported. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | gpio: at91_gpio: remove CPU_HAS_PIO3 macroWenyou Yang2017-04-137-214/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The intention of the removal is the preparation to introduce the new AT91 PIO pinctrl driver. Use the union to make the PIO3 and PIO2's registers be together and make their offset aligned. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | ARM: at91: gpio: fix at91_set_gpio_value() defineWenyou Yang2017-04-131-7/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the CONFIG_ATMEL_LEGACY is undefined, according to the following defines, at91_set_gpio_value() references to at91_set_pio_value(x, y) with two parameters. #define at91_set_gpio_value(x, y) at91_set_pio_value(x, y) #define at91_get_gpio_value(x) at91_get_pio_value(x) But there isn't the implementation of at91_set_pio_value(x, y) with two parameters in U-Boot. This is an error. Same as at91_get_gpio_value(x) define. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2017-04-139-4/+3222
|\ \ | | | | | | | | | | | | | | | Drop CONFIG_STACKSIZE from include/configs/imx6_logic.h Signed-off-by: Tom Rini <trini@konsulko.com>
| * | imx: i.mx6q: add the initial support for LogicPD i.MX6Q SOMAdam Ford2017-04-124-0/+566
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Logic PD has an i.MX6Q system on module (SOM) with a development kit. The SOM has a built-in microSD socket, DDR and NAND flash. The development kit has an SMSC Ethernet PHY, serial debug port and a variety of peripherals. This have been verified to boot the i.MX6Q version over either SD on the development kit or NAND built into the SOM. Items in the dtsi file are specific to the SOM itself. Items in the dts file are in the baseboard. Future versions of the SOM will come out supporting the same basebord and potentially future base boards will come out supporting the same SOM. Signed-off-by: Adam Ford <aford173@gmail.com>
| * | imx: mx7ulp: Fix SPLL/APLL clock rate calculation issueYe Li2017-04-121-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | The num/denom is a float value, but in the calculation it is convert to integer 0, and wrong result. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | ARM: mx5: Rename M53EVKMarek Vasut2017-04-051-1/+1
| | | | | | | | | | | | | | | | | | The board is now manufactured by Aries Embedded GmbH , rename it. Signed-off-by: Marek Vasut <marex@denx.de>
| * | ARM: mxs: Rename M28EVKMarek Vasut2017-04-051-1/+1
| | | | | | | | | | | | | | | | | | The board is now manufactured by Aries Embedded GmbH , rename it. Signed-off-by: Marek Vasut <marex@denx.de>
| * | configs: imx6: Select missing BOARD_LATE_INITJagan Teki2017-03-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Select missing BOARD_LATE_INIT from configs/ to respective targets on arch area for Engicam imx6 boards. Cc: Tom Rini <trini@konsulko.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | imx: mx6slevk: introduce device tree supportPeng Fan2017-03-204-0/+2646
| | | | | | | | | | | | | | | | | | | | | | | | Introduce device tree support. dts from kernel commit c4f3f22edd Merge tag 'linux-kselftest-4.11-rc1' Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | | sandbox: Change CONFIG_SANDBOX_BITS_PER_LONG to hard-codedTom Rini2017-04-131-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of having CONFIG_SANDBOX_BITS_PER_LONG in sandbox.h set to 64 with a comment to change to 32 on a 32bit host, simply set this to 64 in asm/types.h and have the comment be there. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | | board_f: Rename initdram() to dram_init()Simon Glass2017-04-1312-19/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | This allows us to use the same DRAM init function on all archs. Add a dummy function for arc, which does not use DRAM init here. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Dummy function on nios2] Signed-off-by: Tom Rini <trini@konsulko.com>
* | | arm: freescale: Rename initdram() to fsl_initdram()Simon Glass2017-04-121-1/+2
| | | | | | | | | | | | | | | | | | | | | This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Rename aes.h to uboot_aes.hStefano Babic2017-04-121-1/+1
| |/ |/| | | | | | | | | | | | | | | aes.h is a too generic name if this file can be exported and used by a program. Rename it to avoid any conflicts with other files (for example, from openSSL). Signed-off-by: Stefano Babic <sbabic@denx.de>
* | ARCv2: SLC: Make sure busy bit is set properly on SLC flushingAlexey Brodkin2017-04-111-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As reported in STAR 9001165532, an SLC control reg read (for checking busy state) right after SLC invalidate command may incorrectly return NOT busy causing software to NOT spin-wait while operation is underway. (and for some reason this only happens if L1 cache is also disabled - as required by IOC programming model) Suggested workaround is to do an additional Control Reg read, which ensures the 2nd read gets the right status. Same fix made in Linux kernel: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c70c473396cbdec1168a6eff60e13029c0916854 Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2017-04-109-1/+349
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| * | x86: Introduce minimal PMU driver for Intel MID platformsAndy Shevchenko2017-04-104-0/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This simple PMU driver allows to tyrn power on and off for selected devices. In particularly Intel Tangier needs to power on SDHCI controllers in order to access to them during board initialization. In the future it might be expanded to cover other Intel MID platforms, that's why it's located under arch/x86/lib and called pmu.c. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Add SCU IPC driver for Intel MID platformsFelipe Balbi2017-04-105-0/+200
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel MID platforms have few microcontrollers inside SoC, one of them is so called System Controller Unit (SCU). Here is the driver to communicate with microcontroller. Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | x86: bootm: Fix FIT image booting on x86Stefan Roese2017-04-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Checking 'is_zimage' at this time will always fail and therefore booting a FIT style image will always lead to this error message: "## Kernel loading failed (missing x86 kernel setup) ..." This change now removes this check and booting of FIT images works just fine. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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