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* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-12-074-7/+83
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| * armv8: LS1088A_QSPI: SECURE_BOOT: Images validationUdit Agarwal2017-12-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Validates PPA, MC, DPC, Bootscript, DPL and Kernel images in ESBC phase using esbc_validate command. Enable validation of boot.scr script prior to its execution dependent on "secureboot" flag in environment Add header address for PPA to be validated during ESBC phase for LS1088A platform based on LAyerscape Chasis 3. Moves sec_init prior to ppa_init as for validation of PPA sec must be initialised before the PPA is initialised. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: Workaround for USB erratua on LS1012ARan Wang2017-12-062-7/+24
| | | | | | | | | | | | | | | | This is suplement for patch which handle below errata: A-009007, A-009008, A-008997, A-009798 Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Add support of disabling core prefetchPrabhakar Kushwaha2017-12-062-0/+58
| | | | | | | | | | | | | | | | | | | | Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8: fix gd after relocationYork Sun2017-12-071-2/+3
| | | | | | | | | | | | | | | | | | | | Commit 21f4486faa5d ("armv8: update gd after relocate") sets x18 without checking the return value of spl_relocate_stack_gd(). Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: York Sun <york.sun@nxp.com> CC: Kever Yang <kever.yang@rock-chips.com> CC: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | Revert "sandbox: remove os_putc() and os_puts()"Simon Glass2017-12-071-0/+11
|/ | | | | | | | | | | | | While sandbox works OK without the special-case code, it does result in console output being stored in the pre-console buffer while sandbox starts up. If there is a crash or a problem then there is no indication of what is going on. For ease of debugging it seems better to revert this change. This reverts commit 47b98ad0f6779485d0f0c14f337c3eece273eb54. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-uniphierTom Rini2017-12-043-7/+4
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| * mtd: nand: Rename nand.h into rawnand.hMasahiro Yamada2017-12-042-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This header was renamed to rawnand.h in Linux. The following is the corresponding commit in Linux. commit d4092d76a4a4e57b65910899948a83cc8646c5a5 Author: Boris Brezillon <boris.brezillon@free-electrons.com> Date: Fri Aug 4 17:29:10 2017 +0200 mtd: nand: Rename nand.h into rawnand.h We are planning to share more code between different NAND based devices (SPI NAND, OneNAND and raw NANDs), but before doing that we need to move the existing include/linux/mtd/nand.h file into include/linux/mtd/rawnand.h so we can later create a nand.h header containing all common structure and function prototypes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: clean up board_initMasahiro Yamada2017-12-041-5/+2
| | | | | | | | | | | | | | | | Remove unnecessary DECLARE_GLOBAL_DATA_PTR and header includes. <common.h> has been replaced with <linux/errno.h> and <linux/printk.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | arm: Make gcc 6.0 or later a hard requirement now.Tom Rini2017-12-041-2/+2
| | | | | | | | | | | | | | Move the warning to an error as we have been promising would happen in this release. Signed-off-by: Tom Rini <trini@konsulko.com>
* | armv8: mmu: fix page table mappingPeng Fan2017-12-042-1/+5
| | | | | | | | | | | | | | | | | | To page mapping the lowest 2 bits needs to be 0x3. If not fix this, the final lowest 3 bits for page mapping is 0x1 which is marked as reserved. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm64 :show_regs: show the address before relocationPeng Fan2017-12-041-2/+8
| | | | | | | | | | | | | | | | | | | | After relocation, when error happends, it is hard to track ELR and LR with asm file objdumped from elf file. So subtract the gd->reloc_off the reflect the compliation address. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ARM: arch-meson: build memory banks using reported memory from registersNeil Armstrong2017-12-043-8/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As discussed at [1], the Amlogic Meson GX SoCs can embed a BL31 firmware and a secondary BL32 firmware. Since mid-2017, the reserved memory address of the BL31 firmware was moved and grown for security reasons. But mainline U-Boot and Linux has the old address and size fixed. These SoCs have a register interface to get the two firmware reserved memory start and sizes. This patch adds a dynamic reservation of the memory zones in the device tree bootmem reserved memory zone used by the kernel in early boot. To be complete, the memory zones are also added to the EFI reserved zones. Depends on patchset "Add support for Amlogic GXL Based SBCs" at [2]. [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-October/004860.html [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005410.html Changes since v1: - switched the #if to if(IS_ENABLED()) to compile all code paths - renamed function to meson_board_add_reserved_memory() - added a mem.h header with comment - updated all boards ft_board_setup() Changes since RFC v2: - reduced preprocessor load - kept Odroid-C2 static memory mapping as exception Changes since RFC v1: - switch to fdt rsv mem table and efi reserve memory - replaced in_le32 by readl() Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [trini: Fix warning on khadas-vim over missing <asm/arch/mem.h> Signed-off-by: Tom Rini <trini@konsulko.com>
* | arm: Add Khadas VIM support based on Meson GXL familyNeil Armstrong2017-12-043-1/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds platform code for the Khadas VIM board based on a Meson GXL (S905X) SoC with the Meson GXL configuration. This initial submission supports UART, MMC/SDCard and Ethernet with the Internal RMII PHY. The meson-gxl-s905x-khadas-vim.dts is synchronised from the linux 4.13 stable tree as of 4.13.8. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | arm: Add LibreTech CC support based on Meson GXL familyNeil Armstrong2017-12-043-1/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds platform code for the Libre Computer CC "Le Potato" board based on a Meson GXL (S905X) SoC with the Meson GXL configuration. This initial submission supports UART, MMC/SDCard and Ethernet with the Internal RMII PHY. The meson-gxl-s905x-libretech-cc.dts is synchronised from the linux 4.13 stable tree as of 4.13.8. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | ARM: arch-meson: add ethernet common init functionNeil Armstrong2017-12-043-1/+79
| | | | | | | | | | | | | | | | Introduce a generic common Ethernet Hardware init function common to all Amlogic GX SoCs with support for the Internal PHY enable for GXL SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | armv8: shrink exception table codeAndre Przywara2017-12-041-73/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the moment our exception entry code needs 34 instructions, so we can't use put it directly into the table entry, which offers "only" 32 instructions there. Right now we just put an unconditional branch there, then use a macro to place the 34 instructions *per entry* after that. That effectivly doubles the size of our exception table, which is quite a waste, given that we use it mostly for debugging purposes. Since the register saving part is actually identical, let's just convert that macro into a function, and "bl" into it directly from the exception slot, of course after having saved at least the original LR. This saves us about 950 bytes of code, which is quite a relief for some tight SPLs, in particular the 64-bit Allwinner ones. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | add support for Raspberry Pi Zero WDmitry Korunov2017-12-042-0/+42
| | | | | | | | Signed-off-by: Dmitry Korunov <dessel.k@gmail.com>
* | omap2: set the ethaddr as well as the usbethaddr env var to ensure static MACPeter Robinson2017-12-021-0/+3
|/ | | | | | | | | | The kernel gets the ethernet MAC from the ethaddr variable, the omap boards for devices with USB based eth adapters just set the usbethaddr which doesn't appear to get passed to the kernel. The same Raspberry Pi code sets both ethaddr and usbethaddr so lets do that so linux (tested 4.13 and 4.14) get a static rather than a random MAC address, while not regressing users of usbethaddr. Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
* rockchip: clk: rk3128: fix DCLK_VOP_DIV_CON_MASKPhilipp Tomsich2017-12-021-1/+1
| | | | | | | | The DCLK_VOP_DIV_CON_MASK should cover only bits 8 through 15. Fix this to remove an "integer-overflow on shifted constant" warning. Fixes: 9246d9e ("rockchip: rk3128: add clock driver") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: clk: rk3128: fix NANDC_PLL_SEL_MASKPhilipp Tomsich2017-12-021-1/+1
| | | | | | | | The PLL selector field for NANDC is only 2 bits wide. This fixes an 'int-overflow on shift' warning. Fixes: 9246d9e ("rockchip: rk3128: add clock driver") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: dts: rk3399-puma: add /config/sysreset-gpio propertyPhilipp Tomsich2017-11-301-0/+5
| | | | | | | | | | | | | | On the RK3399-Q7, we want to trigger a full platform reset (so the various software stacks supported don't have to deal with the same complexities over and over again) in case that anything other than a power-on reset occurred. To do so, this defines the /config/sysreset-gpio property and has it point to a GPIO that will perform a power-on reset of the entire platform. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
* rockchip: dts: rk3399-puma: add a 'tsd, usb-port-power' stringlist for USB1Philipp Tomsich2017-11-301-0/+1
| | | | | | | | | | | | | | | | USB1 is connected to the on-module USB 3.0 hub and power to the hub (actually it's a reset signal, modeled as a fixed regulator, that will be released) should be enabled only during the first probing of the device to avoid the hub from entering its low-power mode (where it tries to attach on a fixed interval, but we always miss the timeslot when U-Boot has the controller listening). This adds a 'tsd,usb-port-power' stringlist to enable the infrastructure in the board-specific usb_hub_reset_devices to find and control the fixed regulator associated with control of the USB hub. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
* rockchip: rk3036: sdram: correct setting for pll integer modeKever Yang2017-11-301-1/+1
| | | | | | | | | According to rk3036 TRM, should be set to '1' for the pll integer mode, while the '0' means the frac mode. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3036: update clock driver for ddrKever Yang2017-11-301-9/+6
| | | | | | | | | | After the MASK MACRO update, we need to update the driver at the same time. This is a fix to: 37943aa rockchip: rk3036: clean mask definition for cru reg Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3036: fix pll config for correct frequencyKever Yang2017-11-301-2/+3
| | | | | | | | | | There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy, so we need to double to pll output and then ddr can work in correct frequency. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3128: add evb-rk3128 supportKever Yang2017-11-301-0/+24
| | | | | | | | | | | | | | evb-rk3128 is an evb from Rockchip based on rk3128 SoC: - 2 USB2.0 Host port; - 1 HDMI port; - 2 10/100M eth port; - 2GB ddr; - 16GB eMMC; - UART to USB debug port; Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3128: add pinctrl driverKever Yang2017-11-301-0/+551
| | | | | | | | Add rk3128 pinctrl driver and grf/iomux structure definition. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3128: add clock driverKever Yang2017-11-303-0/+245
| | | | | | | | Add rk3128 clock driver and cru structure definition. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3128: add soc basic supportKever Yang2017-11-307-0/+180
| | | | | | | | | | RK3128 is a SoC from Rockchip with quad-core Cortex-A7 CPU and mali400 GPU. Support Nand flash, eMMC, SD card, USB 2.0 host and device, HDMI/LVDS/MIPI display. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3128: add device tree fileKever Yang2017-11-303-0/+900
| | | | | | | | | | | | | | Add dts binding header for rk3128, files origin from kernel. Series-Changes: 2 - fix i2c address - add saradc and usb phy node - emmc using fifo mode for there is no dma support in rk3128 emmc - add some clock id in cru.h Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-shTom Rini2017-11-3019-12522/+168
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| * ARM: rmobile: Rework the ULCB CPLD driverMarek Vasut2017-11-301-0/+9
| | | | | | | | | | | | | | | | Rework the ULCB CPLD driver and make it into a sysreset driver, since that is what the ULCB CPLD driver is mostly for. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Migrate boards to RCar IIC driversMarek Vasut2017-11-301-0/+4
| | | | | | | | | | | | | | | | | | Stop using the old ad-hoc SH I2C driver and use the new RCar IIC driver instead. The SH I2C driver should be deprecated and removed eventually. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Use PRR driver on all Gen3 boardsMarek Vasut2017-11-302-0/+2
| | | | | | | | | | | | | | | | | | Mark the PRR as u-boot,dm-pre-reloc in all Gen3 board DTs as it is needed very early and turn on the CONFIG_SYSCON to allow the PRR driver to bind as a syscon uclass. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Convert PRR to DM and OF controlMarek Vasut2017-11-301-4/+57
| | | | | | | | | | | | | | | | | | | | | | Implement DM driver for the Renesas PRR into RCar cpu info and convert all users with DM and OF enabled to this new driver. This means all of the boards with DM and OF enabled can fetch PRR address from DT, which is useful on ie. V3M which has different PRR address than the rest of Gen3 SoCs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Zap checkboard on Gen3Marek Vasut2017-11-301-0/+2
| | | | | | | | | | | | | | | | | | | | The checkboard() function showing hard-coded board model for which the U-Boot was built is superseded on Gen3 by show_board_info() displaying the Model from device tree. Add small ifdef to stop compiling the function into U-Boot. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Unify R8A7795 and R8A7796 in rmobile MakefileMarek Vasut2017-11-301-2/+1
| | | | | | | | | | | | | | | | Since both R8A7795 and R8A7796 now use the same files, unify the Makefile entry to CONFIG_RCAR_GEN3. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Unify memory map for RCar Gen3Marek Vasut2017-11-306-62/+72
| | | | | | | | | | | | | | | | | | | | Unify the R7A7795 and R8A7796 memory maps in memmap-gen3 and, for now, select which one is used based on which SoC is selected. Since this is done in C code instead of statically assigned now, the decision can be taken by PRR SoC match as well, which will be done in a subsequent patch. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Add PRR CPU ID macrosMarek Vasut2017-11-302-9/+20
| | | | | | | | | | | | | | | | | | | | Replace the ad-hoc values in the PRR CPU ID table with macros, so that users can use rmobile_get_cpu_type() can compare the returned value with these macros to figure out on which CPU they are running. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Dispose of r8a779x.h for Gen3Marek Vasut2017-11-303-62/+2
| | | | | | | | | | | | | | These files no longer contain anything useful, so remove them. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Zap Gen3 PFC tablesMarek Vasut2017-11-306-12366/+2
| | | | | | | | | | | | | | | | These old PFC tables are no longer needed as there is now a proper PFC pinmux driver in drivers/pinctrl/renesas . Remove them . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Drop SDHI address macros from Gen3Marek Vasut2017-11-303-20/+0
| | | | | | | | | | | | | | | | | | Since the RCar Gen3 no longer uses the SH SDHI driver, but rather uses the Matsushita SD driver, which loads all the properties from device tree, these macros are no longer used, remove them. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Fix eMMC signal voltage on ULCBMarek Vasut2017-11-301-1/+1
| | | | | | | | | | | | | | | | The eMMC is 1V8 device only and the signaling is always 1V8, fix the DT for ULCB to describe the hardware correctly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge git://git.denx.de/u-boot-marvellTom Rini2017-11-303-3/+44
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| * | arm: mvebu: enable boot from NANDSean Nyekjaer2017-11-302-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | Check if we are booting from NAND and let the bootrom continue to load the rest of the bootloader Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: fix boot from UART when in fallback modeSean Nyekjaer2017-11-302-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | It's the first 8 bits of the bootrom error register that contain the boot error/fallback error code. Let's check that and continue to boot from UART. Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: add nand pinsSean Nyekjaer2017-11-301-1/+14
| |/ | | | | | | | | Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2017-11-307-43/+118
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| * | x86: lib: Implement standalone __udivdi3 etc instead of libgcc onesStefan Roese2017-11-304-39/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the inclusion of the libgcc math functions and replaces them by functions coded in C, taken from the coreboot project. This makes U-Boot building more independent from the toolchain installed / available on the build system. The code taken from coreboot is authored from Vadim Bendebury <vbendeb@chromium.org> on 2014-11-28 and committed with commit ID e63990ef [libpayload: provide basic 64bit division implementation] (coreboot git repository located here [1]). I modified the code so that its checkpatch clean without any functional changes. [1] git://github.com/coreboot/coreboot.git Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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