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* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqWIP/20May2020Tom Rini2020-05-2046-310/+1201
|\ | | | | | | | | | | | | - Add DM_ETH support for lx2160aqds, ls2080aqds, ls1088aqds - QSI related fixes on ls1012a, ls2080a, ls1046a, ls1088a, ls1043a based platforms - Bug-fixes/updtaes related to ls1046afrwy, fsl-mc, msi-map property
| * arm: dts: ls2080aqds: add CONFIG_MULTI_DTB_FIT supportIoana Ciornei2020-05-195-70/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for selecting the appropriate DTS file depending on the SERDES protocol used. The fsl-ls2080a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol. This patch adds the necessary DPMAC nodes (DPMAC 1-8) for protocol 42 (0x2A) on SD#1. Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arm: dts: ls1088aqds: add CONFIG_MULTI_DTB_FIT supportIoana Ciornei2020-05-197-120/+271
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for selecting the appropriate DTS file depending on the SERDES protocol used. The fsl-ls2088a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol. This patch adds support for the on-board ports (DPMAC 1,2 and 4,5) found on the SERDES protocols 21(0x15) and 29(0x1d) for SD#1. On the LS1088AQDS board EMDIO1 is used with two onboard RGMII PHYs (Realtek RTL8211FD-CG), as well as 2 input/output connectors for mezzanine cards. Configuration signals from the Qixis FPGA control the routing of the external MDIOs. Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one of the 2 IO slots. As a consequence, a new node is added to describe register 0x54 as a MDIO mux controlled with child nodes describing all the IO slots as MDIO buses. Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arm: dts: lx2160aqds: add nodes describing possible mezzanine cardsIoana Ciornei2020-05-1916-178/+670
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device trees describing possible uses of mezzanine cards depending on the SERDES protocol employed. This patch adds DPAA2 networking support for the following protocols on each SERDES block: * SD #1: 3, 7, 19, 20 * SD #2: 11 Each SERDES block has a different device tree file per protocol supported, where the IO SLOTs used are enabled and PHYs located on the mezzanine cards are described. Also, dpmac nodes are edited and their associated phy-connection-type and phy-handle are added. Top DTS files are also added for each combination of protocol on the 3 SERDES blocks. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arm: dts: lx2160aqds: add MDIO slotsIoana Ciornei2020-05-191-1/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LX2160A processor has two external MDIO interfaces, described in the DTS as emdio1 and emdio2. On the LX2160AQDS board EMDIO1 is used with two onboard RGMII PHYs (Realtek RTL8211FD-CG), as well as eight input/output connectors for mezzanine cards. Configuration signals from the Qixis FPGA control the routing of the external MDIOs. Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one of the 8 IO slots. As a consequence, a new node is added to describe register 0x54 as a MDIO mux controlled with child nodes describing all the IO slots as MDIO buses. Also, DPMAC 17 and 18 are updated to reference the on-board PHYs. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arm: dts: lx2160a: add noted for dpmacs 1, 2, 5-6Ioana Ciornei2020-05-191-1/+85
| | | | | | | | | | | | | | | | | | Add nodes for DPMACs 1, 2 and 5-6 which were missing from the description. These will be later used on the LX2160AQDS specific DTS. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * treewide: Update fsl qspi node dt properties as per spi-mem driverKuldeep Singh2020-05-1919-56/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | According to new qspi driver, some properties like "bus-num, num-cs, big-endian" are no longer used. Device endiannes can be determined from device-type data in driver. Now use board specific compatibles, generic node names and specific labels to align with linux device-tree properties. Also consolidate spi-max-frequency to 50Mhz treewide. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * treewide: Remove unused FSL QSPI config options for Layerscape platformsKuldeep Singh2020-05-192-2/+0
| | | | | | | | | | | | | | | | | | | | | | Some of these options are not used by the driver anymore and some of them are obsolete as the information is gathered from the dt. Also consolidating defines in common headers. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | mpc83xx, abb: remove suvd3 boardHeiko Schocher2020-05-191-4/+0
| | | | | | | | | | | | | | | | | | | | the mpc83xxx suvd3 variant is not longer used, so remove it. Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com> Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | mpc83xx: remove redundant MPC83xx_RESET #defineRasmus Villemoes2020-05-191-24/+0
| | | | | | | | | | | | | | | | This macro is only used (tested for existence) in mpc83xx.c, which unconditionally includes mpc83xx.h where it is unconditionally defined. Removing it makes the remaining code easier to read. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
* | common: Drop linux/bitops.h from common headerWIP/2020-05-18-reduce-size-of-common.hSimon Glass2020-05-18192-4/+370
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Use __ASSEMBLY__ as the assembly macrosSimon Glass2020-05-1814-17/+17
| | | | | | | | | | | | | | Some places use __ASSEMBLER__ instead which does not work since the Makefile does not define it. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop linux/delay.h from common headerSimon Glass2020-05-18153-1/+154
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Fix some checkpatch warnings in calls to udelay()Simon Glass2020-05-181-1/+1
| | | | | | | | | | | | | | Fix up some incorrect code style in calls to functions in the linux/time.h header, mostly udelay(). Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop linux/stringify.h from common headerSimon Glass2020-05-182-0/+2
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop linux/bug.h from common headerSimon Glass2020-05-185-0/+5
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop asm_offsets.h from common headerSimon Glass2020-05-185-0/+5
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop asm/ptrace.h from common headerSimon Glass2020-05-1829-0/+29
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop log.h from common headerSimon Glass2020-05-18292-0/+293
| | | | | | | | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Fix some checkpatch warnings in calls to debug()Simon Glass2020-05-181-5/+5
| | | | | | | | | | | | | | Fix up some incorrect code style in calls to functions in the log.h header, mostly debug(). Signed-off-by: Simon Glass <sjg@chromium.org>
* | command: Remove the cmd_tbl_t typedefSimon Glass2020-05-1895-147/+223
| | | | | | | | | | | | | | | | | | | | | | | | | | We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop init.h from common headerSimon Glass2020-05-18229-1/+230
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop image.h from common headerSimon Glass2020-05-1834-0/+38
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop bootstage.h from common headerSimon Glass2020-05-1820-1/+21
| | | | | | | | | | | | Move this fairly uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | bootstage: Use BOOTSTAGE instead of BOOTSTATESimon Glass2020-05-182-4/+4
| | | | | | | | | | | | Some of the enum members are wrong. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop part.h from common headerSimon Glass2020-05-184-0/+6
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | part: Drop disk_partition_t typedefSimon Glass2020-05-183-2/+3
| | | | | | | | | | | | | | We should not be using typedefs and these make it harder to use forward declarations (to reduce header file inclusions). Drop the typedef. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop net.h from common headerSimon Glass2020-05-18111-1/+119
| | | | | | | | | | | | | | | | | | | | | | Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Don't include common.h in header filesSimon Glass2020-05-1860-88/+33
| | | | | | | | | | | | | | | | | | | | | | It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop flash.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | | | | | | | | | | | Move this uncommon header out of the common header. Fix up some style problems in flash.h while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
* | flash: Tidy up coding style for flash functionsSimon Glass2020-05-181-4/+4
|/ | | | | | | Some functions use the wrong code style and generate checkpatch errors. Fix these. Signed-off-by: Simon Glass <sjg@chromium.org>
* dts: nxp2160ardb: add op-tee nodeIlias Apalodimas2020-05-171-0/+6
| | | | | | | A defconfig is added on lx2160ardb which allows UEFI variable management via OP-TEE. Enable the the node in the relevant DTS file. Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
* efi_loader: round the memory area in efi_add_memory_map()Michael Walle2020-05-174-19/+9
| | | | | | | | | | | | | | | | | Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* spl: Always define preloader_console_initSamuel Holland2020-05-152-4/+1
| | | | | | | | | | | | | | | A large number of boards call preloader_console_init unconditionally. Currently, they fail to build with CONFIG_SPL_SERIAL=n, because the function is undefined in that case. To fix the build, always define preloader_console_init, but make it no-op when CONFIG_SPL_SERIAL=n. For the few boards that did check for CONFIG_SPL_SERIAL before calling preloader_console_init, remove the checks, since the function can now be called unconditionally. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* rename symbol: CONFIG_STM32 -> CONFIG_ARCH_STM32Trevor Woerner2020-05-153-3/+3
| | | | | | Have this symbol follow the pattern of all other such symbols. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* rename symbol: CONFIG_TEGRA -> CONFIG_ARCH_TEGRATrevor Woerner2020-05-156-9/+8
| | | | | | Have this symbol follow the pattern of all other such symbols. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* rename symbol: CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOODTrevor Woerner2020-05-156-11/+10
| | | | | | | | Have this symbol follow the pattern of all other such symbols. This patch also removes a TODO from the code. Reviewed-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* arm: orion5x: finish moving SoC to mach-orion5xTrevor Woerner2020-05-151-0/+0
| | | | | | | | The SPL linker script had been left in arch/$(ARCH)/cpu/$(CPU)/$(SOC); therefore move it to the already-established arch/$(ARCH)/mach-$(SOC) location. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* rename symbol: CONFIG_ORION5X -> CONFIG_ARCH_ORION5XTrevor Woerner2020-05-153-4/+3
| | | | | | | Have this symbol follow the pattern of all other such symbols. This patch removes a TODO from the code. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* arch/arm/Makefile: sort machine namesTrevor Woerner2020-05-151-6/+6
| | | | | | | | | | | | The comment immediately above the block of machine directory names implored users to keep the macro names sorted, but, alas, this is no longer the case. Put the list of machine directory names back in alphanumerical order by CONFIG_* macro name, as the comment asks. Sort all the symbols as though they all followed the convention of having the string "ARCH_" in the middle of their definitions. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* arm: lpc32xx: move SoC to mach-lpc32xxTrevor Woerner2020-05-1511-2/+2
| | | | | | | | | | | | | | | | | | Following the example of most other SoCs in arch/$(ARCH)/cpu/$(CPU)/$(SOC) move the lpc32xx code from arch/arm/cpu/arm926ejs/lpc32xx to arch/arm/mach-lpc32xx. Following the checklist from commit 01f14456306c ("ARM: prepare for moving SoC sources into mach-*"): [1] move files from arch/arm/cpu/arm926ejs/lpc32xx to arch/arm/mach-lpx32xx [2] add machine entry to arch/arm/Makefile [3] remove "obj-y += ..." from arch/arm/cpu/arm926ejs/Makefile [4] fix the Kconfig file path in arch/arm/Kconfig [5] (no MAINTAINERS update) Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* Merge tag 'u-boot-stm32-20200514' of ↵WIP/14May2020Tom Rini2020-05-1438-257/+4414
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-stm - stm32mp1: migrate MTD and DFU configuration in Kconfig - stm32mp1: add command stm32prog - stm32mp1: several board and arch updates - stm32mp1: activate data cache in SPL and before relocation - Many improvment for AV96 board and DHCOR SoM (add new defconfig, DDR3 coding on DHCOR SoM, split between board and SOM Synchronize DDR setttings on DH SoMs, setting for I2C EEPROM) - clk: stm32mp1: fix CK_MPU calculation - DT alignment of stm32mp1 device tree with Linux 5.7-rc2
| * ARM: dts: stm32mp1: DT alignment with Linux 5.7-rc2Patrick Delaunay2020-05-148-26/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DT alignment with Linux 5.7-rc2, including the kernel commits 431c89e6f323 ARM: dts: stm32: use correct vqmmc regu for eMMC on stm32mp1 ED1/EV1 boards 79e965053872 ARM: dts: stm32: add disable-wp property for SD-card on STM32MP1 boards 877db62ea516 ARM: dts: stm32: add cd-gpios properties for SD-cards on STM32MP1 boards 7519e95ba5f8 ARM: dts: stm32: Do clean up in stmpic nodes on stm32mp15 boards f68e2dbc591a ARM: dts: stm32: Rename stmfx joystick pins on stm32mp157c-ev1 d6210da4f8bf ARM: dts: stm32: add cpu clock-frequency property on stm32mp15x b65b6fc56925 ARM: dts: stm32: add wakeup-source in all I2C nodes of stm32mp157c 1c1cf5996cfb ARM: dts: stm32: add i2c4 sleep pinctrl on stm32mp157c-ed1 bef15fc0fad9 ARM: dts: stm32: add i2c2/i2c5 sleep pinctrl on stm32mp157c-ev1 b7fc0a87b9ac ARM: dts: stm32: add i2c4 sleep pinctrl on stm32mp15xx-dkx a5e557655285 ARM: dts: stm32: set i2c4 bus freq to 400KHz on stm32mp15 DK boards 8bc631b650a6 ARM: dts: stm32: set i2c4 bus freq to 400KHz on stm32mp157c-ed1 fccd6a577bb3 ARM: dts: stm32: Correct stmfx node name on stm32mp157c-ev1 board cc775a83db65 ARM: dts: stm32: add resets property on all DMA nodes on stm32mp151 c5fae093511b ARM: dts: stm32: enable USB OTG Dual Role on stm32mp157c-ev1 9879e2165758 ARM: dts: stm32: add USB OTG pinctrl to stm32mp15 82ac8a81f985 ARM: dts: stm32: add USB OTG full support on stm32mp151 8714b26e2863 ARM: dts: stm32: remove useless properties in stm32mp157a-avenger96 stmpic node a7959919709e ARM: dts: stm32: Add UART8 pins A pinmux entry on stm32mp1 4d7c53a684da ARM: dts: stm32: Add USART3 pins A pinmux entry on stm32mp1 80ab128332ee ARM: dts: stm32: Add SAI2A pins B pinmux entry on stm32mp1 ab7f98c0c546 ARM: dts: stm32: Add Ethernet0 RMII pins A pinmux entry on stm32mp1 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * arm: stm32mp: activate data cache on DDR in SPLPatrick Delaunay2020-05-141-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Activate cache on DDR to improve the accesses to DDR used by SPL: - CONFIG_SPL_BSS_START_ADDR - CONFIG_SYS_SPL_MALLOC_START Cache is configured only when DDR is fully initialized, to avoid speculative access and issue in get_ram_size(). Data cache is deactivated at the end of SPL, to flush the data cache and the TLB. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * arm: stm32mp: activate data cache in SPL and before relocationPatrick Delaunay2020-05-141-1/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Activate the data cache in SPL and in U-Boot before relocation. In arch_cpu_init(), the function early_enable_caches() sets the early TLB, early_tlb[] located .init section, and set cacheable: - for SPL, all the SYSRAM - for U-Boot, all the DDR After relocation, the function enable_caches() (called by board_r) reconfigures the MMU with new TLB location (reserved in board_f.c::reserve_mmu) and re-enable the data cache. This patch allows to reduce the execution time, particularly - for the device tree parsing in U-Boot pre-reloc stage (dm_extended_scan_fd =>dm_scan_fdt) - in I2C timing computation in SPL (stm32_i2c_choose_solution()) For example, the result on STM32MP157C-DK2 board is: 1,6s gain for trusted boot chain with TF-A 2,2s gain for basic boot chain with SPL For information, as TLB is added in .data section, the binary size increased and the SPL load time by ROM code increased (30ms on DK2). But early malloc can't be used for TLB because arch_cpu_init() is executed before the early poll initialization done in spl_common_init() called by spl_early_init() So it too late for this use case. And if I initialize the MMU and the cache after this function it is too late, as dm_init_and_scan and fdt parsing is also called in spl_common_init(). And .BSS can be used in board_init_f(): only stack and global can use before BSS init done in board_init_r(). So .data is the better solution without hardcoded location but if you have size issue for SPL you can deactivate cache for SPL only (with CONFIG_SPL_SYS_DCACHE_OFF). Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * ARM: stm32: Hog GPIO PF7 high on DHCOM to unlock SPI NOR nWPMarek Vasut2020-05-141-0/+9
| | | | | | | | | | | | | | | | | | | | The SPI NOR nWP line is connected to GPIO PF7 on the SoM, pull the GPIO line high by default to clear SPI NOR WP. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
| * ARM: dts: stm32: Synchronize DDR setttings on DH SoMsMarek Vasut2020-05-145-4/+366
| | | | | | | | | | | | | | | | | | | | | | Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put them into use by the board file instead of the default ones. These new DRAM settings are a better fit for the SoMs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
| * ARM: dts: stm32: Fix AV96 and DHCOR splitMarek Vasut2020-05-143-13/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board") was not applied correctly and in full, and omitted an important split of the SoM into 3V3 and 1V8 options. The Avenger96 board is based on the 1V8 IO option of the DHCOR SoM, however this is an optional modification of the 3V3 IO DHCOR SoM with extra on-SoM regulator to cater for the 96boards 1V8 IO requirements. Reinstate the split between the 1V8 and 3V3 IO variants. Fixes: 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
| * ARM: dts: stm32mp15: use DDR3 files generated by STM32CubeMXPatrick Delaunay2020-05-142-50/+46
| | | | | | | | | | | | | | | | | | Use the DDR3 dtsi files generated by STM32CubeMX 5.6.0 Speed Bin Grade = using DDR3-1066G / 8-8-8 and all others parameters at default value. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * board: stm32mp1: update management of boot-ledPatrick Delaunay2020-05-142-8/+0
| | | | | | | | | | | | | | Force boot-led ON and no more rely on default-state. This patch avoid device-tree modification for U-Boot. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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